P87C660X2 PHILIPS [NXP Semiconductors], P87C660X2 Datasheet - Page 38

• Manufacturer Part Number: P87C660X2
• Description: 80C51 8-bit microcontroller family
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
If the STA and STO bits are both set, the a STOP condition is
transmitted to the I
mode, SIO1 generates an internal STOP condition which is not
transmitted). SIO1 then transmits a START condition.
STO = “0”: When the STO bit is reset, no STOP condition will be
generated.
SI
SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible SIO1 states is
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A HIGH level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA
AA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line
when:
– The “own slave address” has been received
– The general call address has been received while the general call
– A data byte has been received while SIO1 is in the master
– A data byte has been received while SIO1 is in the addressed
AA = “0”: if the AA flag is reset, a not acknowledge (HIGH level to
SDA) will be returned during the acknowledge clock pulse on SCL
when:
– A data has been received while SIO1 is in the master receiver
– A data byte has been received while SIO1 is in the addressed
When SIO1 is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 25).
When SI is cleared, SIO1 leaves state C8H, enters the not
addressed slave receiver mode, and the SDA line remains at a
HIGH level. In state C8H, the AA flag can be set again for future
address recognition.
When SIO1 is in the not addressed slave mode, its own slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, SIO1 can be temporarily released from the I
2003 Oct 02
, THE
bit (GC) in S1ADR is set
receiver mode
slave receiver mode
mode
slave receiver mode
80C51 8-bit microcontroller family
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
, THE
S
A
ERIAL
SSERT
I
NTERRUPT
A
CKNOWLEDGE
2
C bus if SIO1 is in a master mode (in a slave
2
C interfaces
F
LAG
F
LAG
16 KB OTP/ROM, 512B
2
C bus while the
38
The frequencies shown in Table 7 are unimportant when SIO1 is in a
slave mode. In the slave modes, SIO1 will automatically synchronize
bus status is monitored. While SIO1 is released from the bus,
START and STOP conditions are detected, and serial data is shifted
in. Address recognition can be resumed at any time by setting the
AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will
be recognized at the end of the byte transmission.
CR
These three bits determine the serial clock frequency when SIO1 is
in a master mode. The various serial rates are shown in Table 7.
For the SIO1 serial port, the Standard data transfer mode is the
default mode after reset. To change the data transfer mode to the
Fast–mode, the Fast Mode Enable bit (FME bit) of the AUXR
Register (AUXR.3 bit) must be set. After setting the FME bit you
cannot clear it (a one–time set bit), and it can only be cleared with
a reset.
For the SIO2 serial port, the analog circuits for controlling the
slew–rates of the output pull-downs may be disabled with the
Slew–Rate Disable bit (AUXR.5 bit). For maximum slew rates,
setting this bit disables the slew–rate control circuits of the SCL1
and SDA1 pins. This bit is cleared by reset (reset default), and it
can be set/cleared by software. This feature of the SIO2 slew–rate
control is very useful for higher bus loads, higher temperatures and
lower voltages that cause additional decreases in slew–rates.
A 12.5kHz bit rate may be used by devices that interface to the I
bus via standard I/O port lines which are software driven and slow.
100kHz is usually the maximum bit rate and can be derived from a
16 MHz, 12 MHz, or a 6 MHz oscillator. A variable bit rate (0.5kHz to
62.5kHz) may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
with any clock frequency up to 100kHz.
The Status Register, S1STA: S1STA is an 8-bit read-only special
function register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined SIO1 states. When each of
these states is entered, a serial interrupt is requested (SI = “1”). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
AUXR (8EH)
0,
CR
1, AND
CR
7
–
2, THE
6
–
C
LOCK
SRD
5
R
P8xC660X2/661X2
ATE
4
–
B
ITS
FME
3
2
–
TRAM
Product data
EX-
1
A0
2
0
C