LPC2194HBD64 NXP [NXP Semiconductors], LPC2194HBD64 Datasheet - Page 16

• Manufacturer Part Number: LPC2194HBD64
• Description: Single-chip 16/32-bit microcontroller; 256 kB ISP/IAP flash with 10-bit ADC and CAN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2194_5
Product data sheet
6.12.1 Features
6.12.2 Features available in LPC2194/01 only
6.13.1 Features
6.12 SPI serial I/O controller
6.13 SSP controller (LPC2194/01 only)
6.14 General purpose timers
The LPC2194 each contain two SPIs. The SPI is a full duplex serial interface, designed to
be able to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends a byte of data to the slave, and the slave
always sends a byte of data to the master.
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. The application can switch on
the fly from SPI1 to SSP and back.
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
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Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of
Eight to 16 bits per frame.
When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
Rev. 05 — 10 December 2007
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of the input clock rate.
Single-chip 16/32-bit microcontroller
LPC2194
© NXP B.V. 2007. All rights reserved.
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