AT91SAM7S128 ATMEL [ATMEL Corporation], AT91SAM7S128 Datasheet - Page 27

• Manufacturer Part Number: AT91SAM7S128
• Manufacturer: ATMEL [ATMEL Corporation]

10.4
10.5
6175BS–ATARM–04-Nov-05
Power Management Controller
Advanced Interrupt Controller
The Power Management Controller uses the Clock Generator outputs to provide:
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing
reduced power consumption while waiting for an interrupt.
Figure 10-5. Power Management Controller Block Diagram
• the Processor Clock PCK
• the Master Clock MCK
• the USB Clock UDPCK (not present on AT91SAM7S32)
• all the peripheral clocks, independently controllable
• three programmable clock outputs
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Individually maskable and vectored interrupt sources
• 8-level Priority Controller
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.)
– Other sources control the peripheral interrupts or external interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive external
– Drives the normal interrupt of the processor
– Handles priority of the interrupt sources
sources
MAINCK
PLLCK
MAINCK
SLCK
PLLCK
SLCK
PLLCK
Master Clock Controller
Programmable Clock Controller
/1,/2,/4,...,/64
Prescaler
USB Clock Controller
AT91SAM7S Series Summary
/1,/2,/4,...,/64
ON/OFF
Divider
/1,/2,/4
Prescaler
Processor
Controller
Idle Mode
Clock Controller
Clock
Peripherals
ON/OFF
usb_suspend
int
UDPCK
PCK
MCK
periph_clk[2..14]
pck[0..2]
27