AT91SAM7S128 ATMEL [ATMEL Corporation], AT91SAM7S128 Datasheet - Page 16

• Manufacturer Part Number: AT91SAM7S128
• Manufacturer: ATMEL [ATMEL Corporation]

8.4
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Peripheral DMA Controller
AT91SAM7S Series Summary
• Handles data transfer between peripherals and memories
• Eleven channels: AT91SAM7S256/128/64/321
• Nine channels: AT91SAM7S32
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirements
– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for the Serial Peripheral Interface
– One for the Analog-to-digital Converter
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
wait states
6175BS–ATARM–04-Nov-05