DSPIC30F2011 MICROCHIP [Microchip Technology], DSPIC30F2011 Datasheet - Page 114

• Manufacturer Part Number: DSPIC30F2011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F2011/2012/3012/3013
FIGURE 16-2:
16.8
The module has 2 internal Power modes.
When the ADON bit is ‘1’, the module is in Active mode;
it is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The dig-
ital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
16.9
16.9.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The A/D module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the RC
clock source is selected, the A/D module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which elim-
inates all digital switching noise from the conversion.
When the conversion is complete, the CONV bit will be
cleared and the result loaded into the ADCBUF register.
DS70139C-page 112
Module Power-down Modes
A/D Operation During CPU Sleep
and Idle Modes
A/D OPERATION DURING CPU
SLEEP MODE
Note: C
Legend: C
VA
PIN
Rs
12-BIT A/D CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
V
I leakage
R
R
C
ANx
PIN
T
IC
SS
HOLD
C
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
V
DD
V
V
T
T
= 0.6V
= 0.6V
Preliminary
R
I leakage
IC
500 nA
250
If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the
D module will then be turned off, although the ADON bit
will remain set.
16.9.2
The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will con-
tinue operation on assertion of Idle mode. If ADSIDL =
1, the module will stop on Idle.
16.10 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off, and any
conversion and sampling sequence is aborted. The val-
ues that are in the ADCBUF registers are not modified.
The A/D Result register will contain unknown data after
a Power-on Reset.
16.11 Output Formats
The A/D result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
Sampling
Switch
R
A/D OPERATION DURING CPU IDLE
MODE
SS
PIN
R
negligible if Rs
SS
V
SS
C
= DAC capacitance
= 18 pF
HOLD
3 k
© 2005 Microchip Technology Inc.
2.5 k .
A/