DSPIC30F2011 MICROCHIP [Microchip Technology], DSPIC30F2011 Datasheet - Page 113

• Manufacturer Part Number: DSPIC30F2011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

16.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
16.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADCBUF will not
be updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If the clearing of the ADON bit coincides with an auto-
start, the clearing has a higher priority and a new
conversion will not start.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
16.6
The A/D conversion requires 14 T
A/D conversion clock is software selected, using a
six-bit counter. There are 64 possible options for T
EQUATION 16-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 667 nsec (for V
Specifications section for minimum T
operating conditions.
© 2005 Microchip Technology Inc.
AD
) must be selected to ensure a minimum T
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the A/D Conversion
Clock
T
AD
= T
CY
DD
* (0.5*(ADCS<5:0> + 1))
A/D CONVERSION CLOCK
= 5V). Refer to the Electrical
AD
. The source of the
AD
dsPIC30F2011/2012/3012/3013
under other
AD
AD
wait is
AD
time
Preliminary
.
Example 16-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 16-1:
16.7
The analog input model of the 12-bit A/D converter is
shown in Figure 16-2. The total sampling time for the A/
D is a function of the internal amplifier settling time and
the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the voltage level on the analog input
pin. The source impedance (R
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D con-
verter, the maximum recommended source imped-
ance, R
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
SS
) impedance combine to directly affect the time
Therefore,
Set ADCS<5:0> = 39
S
A/D Acquisition Requirements
, is 2.5 k . After the analog input channel is
ADCS<5:0> = 2
Minimum T
Actual T
IC
= ~100 kHz
= 1 T
= 15 x 667 nsec
), and the internal sampling switch
AD
T
(15 x 667 nsec)
AD
CY
AD
= 2 •
= 39
=
=
= 667 nsec
A/D CONVERSION CLOCK
AND SAMPLING RATE
CALCULATION
= 667 nsec
= 33 .33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
1
T
T
CY
2
AD
33.33 nsec
CY
667 nsec
2
AD
(ADCS<5:0> + 1)
HOLD
– 1
S
HOLD
), the interconnect
DS70139C-page 111
) must be allowed
(39 + 1)
. The combined
– 1