TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 9

• Manufacturer Part Number: TSI-8
• Description: 8K x 8K Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Hardware Design Guide, Revision 1
November 2, 2005
Table 3-7. Control Port
Table 3-8. Initialization and Test Access
Agere Systems Inc.
Ball Name Type
ADDR[15:00] I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bit for
DATA[15:00]
RSV[11:1]
Ball Name
RESET
TRSTN
MPUCLK
PAR[1:0]
TMS
TDO
TCK
TDI
HIZ
R/W
INT
CS
AS
DT
I pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The reset occurs
I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP) controller.
I pu Test Data In. Data input for the boundary scan. Sampled on the rising edge of TCK. 20 kΩ pull-up
I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled on the rising
I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20 kΩ pull-down
I pu Output Enable. All output and bidrectional buffers will be high impedance when this input is low unless
— Reserved [11:1]. These balls are used by Agere Systems during the manufacturing process. They must
O
Type
O od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. This signal
I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers. The
I/O Control Port Parity [1:0]. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and
O
I
I
I
I
asynchronously, but RESET should be held low for at least two CHICLK periods. 20 kΩ pull-up resistor.
Should be static except during boundary-scan testing. 20 kΩ pull-up resistor.
resistor.
edge of TCK. 20 kΩ pull-up resistor.
resistor.
Test Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except when
scanning out test data.
boundary scan is enabled (TRSTN = 1). 20 kΩ pull-up resistor.
be left unconnected.
Processor Clock. This clock is used to sample address, data, and control signals from the
microprocessor. This clock must be within the range of 0 MHz—66 MHz. Required for operation.
Chip Select. Active-low chip select. This input is held low for the duration of any read or write access
to the TSI-8. Required for operation.
Address Strobe. Active-low address strobe that is one MPUCLK cycle wide at the start of a
microprocessor access cycle to the TSI-8. This is used to initiate a microprocessor access. Required
for operation.
Read/Write. Cycle selection. R/W is set high during a read cycle, or set low for a write cycle.
Required for operation.
addressing all the internal registers during microprocessor access cycles. All addresses are
16-bit word addresses; hence, in a typical application ADDR[00] of the TSI-8 device would be
connected to address bit 1 of a byte addressable system address bus. Required for operation. 200
kΩ pull-up resistor.
Note: The TSI-8 is little-endian; the least significant byte is stored in the lowest address and the most
balls are inputs during write cycles and outputs during read cycles. DATA[15] is the most significant
bit, and DATA[00] is the least significant bit. Required for operation.
PAR[0] is the parity for DATA[7:0]. The parity sense (even or odd) is application programmable via a
register bit in the TSI-8. Not required for operation.
Data Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been
written during write cycles or that data is valid during read cycles. High impedance when CS is a 1
and driven when CS is 0. Required for operation.
remains active-low until the interrupt status register has been cleared or masked.
significant byte is stored in the highest address. Care must be exercised in connection to
microprocessors that use big-endian byte ordering.
Name/Description
Name/Description
8K x 8K Time-Slot Interchanger
TSI-8
9