TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 2

• Manufacturer Part Number: TSI-8
• Description: 8K x 8K Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Contents
TSI-8
8K x 8K Time-Slot Interchanger
1 Introduction .............................................................. 1
2 Description ............................................................... 1
3 Ball Information ........................................................ 3
4 Absolute Maximum Ratings ................................... 11
5 dc Electrical Characteristics .................................. 13
6 Timing Diagrams and ac Characteristics ............... 14
7 Outline Diagrams ................................................... 24
8 Ordering Information .............................................. 25
9 Change History ...................................................... 25
Figures
Figure 2-1. Block Diagram and High-Level Interface
Figure 3-1. Package Diagram (Top View) ................... 3
Figure 6-1. CHICLK Timing Specifications ................ 14
Figure 6-2. MPUCLK Timing Specifications .............. 14
Figure 6-3. ac Timing Specification ........................... 15
Figure 6-4. CHI Interface Timing ............................... 15
Figure 6-5. Typical Receive CHI Timing with 16.384
Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s
Figure 6-7. Typical Receive CHI Timing with 8.192
Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s
Figure 6-9. Typical Receive CHI Timing with 4.096
Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s
Figure 6-11. Typical Receive CHI Timing with 2.048
Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s
2
1.1 Related Documents .......................................... 1
2.1 Block Diagram and High-Level Interface
3.1 Ball Diagram ..................................................... 3
3.2 Package Ball Assignments ............................... 4
3.3 Ball Types ......................................................... 8
3.4 Ball Definitions .................................................. 8
4.1 Handling Precautions ..................................... 11
4.2 ESD Tolerance ............................................... 11
4.3 Package Thermal Characteristics ................... 11
4.4 Recommended Operating Conditions ............ 12
Definition .......................................................... 1
Definition ................................................... 1
Mbits/s Data and 16.384 MHz CHICLK... 16
Data and 16.384 MHz CHICLK ............... 16
Mbits/s Data and 16.384 MHz CHICLK... 17
Data and 16.384 MHz CHICLK ............... 17
Mbits/s Data and 16.384 MHz CHICLK... 18
Data and 16.384 MHz CHICLK ............... 18
Mbits/s Data and 16.384 MHz CHICLK... 19
Data and 16.384 MHz CHICLK ............... 19
Table of Contents
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Contents
Figure 6-13. Typical Receive CHI Timing with 8.192
Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s
Figure 6-15. CHI 3-State Output Control ................... 21
Figure 6-16. Microprocessor Port Timing—
Figure 6-17. Microprocessor Port Timing—
Tables
Table 3-1. Package Ball Assignments in Signal Name
Table 3-2. Package Ball Assignments in Ball Number
Table 3-3. Package Ball Assignments in Ball Number
Table 3-4. Ball Types ................................................... 8
Table 3-5. Timing Port.................................................. 8
Table 3-6. Transmit and Receive Concentration
Table 3-7. Control Port................................................. 9
Table 3-8. Initialization and Test Access...................... 9
Table 3-9. Power Balls............................................... 10
Table 4-1. Absolute Maximum Ratings ...................... 11
Table 4-2. ESD Tolerance.......................................... 11
Table 4-3. Power Consumption ................................. 11
Table 4-4. Operating Conditions ................................ 12
Table 5-1. CMOS Inputs ............................................ 13
Table 5-2. CMOS Outputs ......................................... 13
Table 5-3. CMOS Bidirectionals (Excluding
Table 5-4. CMOS Bidirectionals (TXD[31:00]) ........... 13
Table 6-1. CHICLK Timing Specifications .................. 14
Table 6-2. MPUCLK Timing Specifications ................ 14
Table 6-3. CMOS Output ac Timing Specification * ... 15
Table 6-4. CHI Interface Timing ................................. 15
Table 6-5. CHI 3-State Output Control .......................21
Table 6-6. Microprocessor Port Timing—
Table 6-7. Microprocessor Port Timing—
Table 8-1. Ordering Information................................. 25
Order ........................................................... 4
Order (Top View) ......................................... 6
Order (Bottom View) (continued)................. 7
Highways..................................................... 8
TXD[31:00]) ............................................... 13
Read Cycle................................................ 22
Write Cycle23
Mbits/s Data and 8.192 MHz CHICLK ..... 20
Data and 8.192 MHz CHICLK ................. 20
Read Cycle............................................. 22
Write Cycle............................................. 23
Hardware Design Guide, Revision 1
Agere Systems Inc.
November 2, 2005
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