TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 23

• Manufacturer Part Number: TSI-8
• Description: 8K x 8K Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Hardware Design Guide, Revision 1
November 2, 2005
Table 6-7. Microprocessor Port Timing—Write Cycle
Note: Posted writes follow the same timing shown in Figure 6-17 and Table 6-7. A posted write may return a DT prior to the
Agere Systems Inc.
Parameter
DATA[15:00]
ADDR[15:00]
t
t
t
t
t
t
t
t
t
t
t
t
t
device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the
write.
37
38
39
40
41
42
43
44
45
46
47
48
49
PAR[1:0]
MPUCLK
R/W
DT
CS
AS
Address Setup
Address Hold
Chip Select Setup
Chip Select Hold
Address Strobe Setup
Address Strobe Hold
R/W Setup
R/W Hold
Data Setup
Data Hold
DT High-Impedance to Valid
DT Clock to Out
DT Valid to High-Impedance
Figure 6-17. Microprocessor Port Timing—Write Cycle
t
t
t
t
t
47
37
39
41
43
t
t
38
42
Description
t
45
t
48
8K x 8K Time-Slot Interchanger
Min
5
1
5
1
5
1
5
1
5
1
1
1
1
t
t
t
t
48
44
40
46
Max
15
—
—
—
—
—
—
—
—
—
—
7
8
t
49
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSI-8
23