STTS2002_11 STMICROELECTRONICS [STMicroelectronics], STTS2002_11 Datasheet - Page 34

• Manufacturer Part Number: STTS2002_11
• Description: 2.3 V memory module temperature sensor with a 2 Kb SPD EEPROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPD EEPROM operation
5.5
5.5.1
5.5.2
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Write operations
Following a start condition the bus master sends a device select code with the RW bit reset
to 0. The device acknowledges this, as shown in
The device responds to the address byte with an acknowledge bit, and then waits for the
data byte.
When the bus master generates a stop condition immediately after the ack bit (in the “10
bit” time slot), either at the end of a byte write or a page write, the internal memory write
cycle is triggered. A stop condition at any other time slot does not trigger the internal write
cycle.
During the internal write cycle, serial data (SDA) and serial clock (SCL) are ignored, and the
device does not respond to any requests.
Byte write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoAck, and the location is not modified. If, instead, the addressed location is not write-
protected, the device replies with Ack. The bus master terminates the transfer by generating
a stop condition, as shown in
Page write
The page write mode allows up to 16 bytes to be written in a single write cycle, provided that
they are all located in the same page in the memory: that is, the most significant memory
address bits are the same. If more bytes are sent than will fit up to the end of the page, a
condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become
overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device. After each byte is transferred, the internal byte address counter (the 4 least
significant address bits only) is incremented. The transfer is terminated by the bus master
generating a stop condition.
Figure 12. Write mode sequences in a non write-protected area of SPD
BYTE WRITE
PAGE WRITE
Figure
Doc ID 15389 Rev 5
DEV SEL
DEV SEL
ACK
12.
DATA IN N
R/W
R/W
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
Figure
ACK
ACK
12, and waits for an address byte.
DATA IN 1
DATA IN
ACK
ACK
DATA IN 2
STTS2002
AI01941
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