STTS2002_11 STMICROELECTRONICS [STMicroelectronics], STTS2002_11 Datasheet - Page 20

• Manufacturer Part Number: STTS2002_11
• Description: 2.3 V memory module temperature sensor with a 2 Kb SPD EEPROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Temperature sensor registers
Table 9.
20/52
Bit
0
1
2
3
4
5
6
7
8
Event mode
– 0 = Comparator output mode (this is the default).
– 1 = Interrupt mode; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it is
Event polarity
The event polarity bit controls the active state of the EVENT pin. The EVENT pin is driven to this state
when it is asserted.
– 0 = Active-low (this is the default). Requires a pull-up resistor to set the inactive state of the open-
– 1 = Active-high. The active state of the pin is then logical “1”.
Critical event only
– 0 = Event output on alarm or critical temperature event (this is the default).
– 1 = Event only if the temperature is above the value in the critical temperature register (T
Event output control
– 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it
Event status (read-only)
– 0 = Event output condition is not being asserted by this device.
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
Clear event (write-only)
– 0 = No effect.
– 1 = Clears the active event in interrupt mode. The pin is released and will not assert until a new interrupt
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
Shutdown mode
– 0 = TS is enabled, continuous conversion (this is the default).
– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No
unlocked.
drain output. The power to the pull-up resistor should not be greater than V
is logical “0”.
the alarm window lock bit (bit6) is set, this bit cannot be altered until it is unlocked.
is unlocked.
condition occurs.
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
event conditions will be asserted; when either of the lock bits (bit6 or bit7) is set, then this bit cannot be
altered until it is unlocked. It can be cleared at any time.
Configuration register bit definitions
(1)
(3)
(2)
Doc ID 15389 Rev 5
Definition
DD
+ 0.2 V. Active state
A
> T
CRIT
STTS2002
); when