LM96080CIMT-NOPB1 NSC [National Semiconductor], LM96080CIMT-NOPB1 Datasheet - Page 28

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LM96080CIMT-NOPB1

Manufacturer Part Number
LM96080CIMT-NOPB1
Description
System Hardware Monitor with 2-Wire Serial Interface
Manufacturer
NSC [National Semiconductor]
Datasheet
www.national.com
12.12 Value RAM—Address 20h–3Fh
Address A7–A0
Note: Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when
voltages go below the low limits.
For voltage input high limits, the device is doing a greater than comparison. For low limits, however, it is doing a less than or equal to comparison.
2Ah
2Bh
2Ch
2Dh
2Eh
3Ah
3Bh
3Ch
3Dh
3Eh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Fh
IN0 reading (10-bit)
IN1 reading (10-bit)
IN2 reading (10-bit)
IN3 reading (10-bit)
IN4 reading (10-bit)
IN5 reading (10-bit)
IN6 reading (10-bit)
Temperature reading (9-bit or 12-bit for easy read-back)
FAN1 reading
Note: This location stores the number of counts of the internal clock per revolution.
FAN2 reading
Note: This location stores the number of counts of the internal clock per revolution.
IN0 High Limit
IN0 Low Limit
IN1 High Limit
IN1 Low Limit
IN2 High Limit
IN2 Low Limit
IN3 High Limit
IN3 Low Limit
IN4 High Limit
IN4 Low Limit
IN5 High Limit
IN5 Low Limit
IN6 High Limit
IN6 Low Limit
Hot Temperature Limit (High)
Hot Temperature Hysteresis Limit (Low)
OS Temperature Limit (High)
OS Temperature Hysteresis Limit (Low)
FAN1 Fan Count Limit
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
FAN2 Fan Count Limit
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
Manufacturer's ID always defaults to 0000 0001; this register is writable and can be reset to the default value by
the INITIALIZATION bit in the Configuration Register (address 00h, bit 7).
Stepping/Die Revision ID always defaults to 0000 1000; this register is writable and can be reset to the default
value by the INITIALIZATION bit in the Configuration Register.
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Description

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