LM5069_10 NSC [National Semiconductor], LM5069_10 Datasheet - Page 5

• Manufacturer Part Number: LM5069_10
• Description: Output Voltage Clamping Using the LM5069 Hot Swap Controller
• Manufacturer: NSC [National Semiconductor]

Trace 1: V
Trace 2: GATE pin (20V/div)
Trace 3: TIMER pin (1V/div)
Trace 4: V
Referring to Figure 6, initially V
GATE pin, which would normally be at 60V if Z1 were not
present, is at approximately 55.8V due to Z1. But the gate-to-
source voltage is sufficient to fully enhance Q1’s gate so that
V
TIMER pin is at zero since the load current is below the cur-
rent limit threshold. When V
60V, there is a momentary current surge through R
to the capacitor at V
reached the Circuit Breaker limit of the LM5069, which trig-
gered the strong pull-down at the GATE pin.* This is why the
GATE pin voltage quickly dropped 10V when V
and the voltage at V
current was momentarily reduced. Immediately after that, the
circuit breaker function is shut off (due to the reduced current
level), and the current limit feature of the LM5069 then limits
the current through R
limiting (approximately 2 ms in Figure 6) the voltage at the
TIMER pin increases since current limiting is a fault condition.
As the voltage at V
increases with it until it reaches the clamp voltage set by Z1
(55.8V in Figure 6). At this point the voltage at V
clamped at 51.1V, and remains at that level for the remaining
time that V
the load current (0.213A) is below the current limit threshold,
and the power dissipated in Q1 (1.9W) is below the power
limit threshold. The TIMER pin voltage is decreasing back to-
wards zero volts. When the voltage at V
48V, the voltage at V
voltage remains at 55.8V since V
*The current surge amplitude was verified with a current
probe in series with R
OUT
is not clamped, and is equal to V
OUT
IN
(20V/div)
IN
(20V/div)
is at 60V. During the time that V
OUT
OUT
OUT
OUT
S
S
increases the voltage at the GATE pin
.
and Q1. During this time of current
dropped a small amount as the load
reduces back to 48V. The GATE pin
(C
L
IN
). The current surge amplitude
increases quickly from 48V to
IN
IN
and V
is above 44V.
IN
OUT
. The voltage at the
FIGURE 6. Transient Testing with Z1 = 56V
IN
reduces back to
are at 48V. The
OUT
IN
is clamped,
increased,
S
and Q1
OUT
is
5
Transient Testing and Fault Timeout
In the above two transient tests, the simulated transients were
repetitive with V
lower level for 80 ms. The LM5069 did not produce a fault
timeout since the TIMER pin voltage, which increased during
the brief current limiting period, was able to reduce to zero
before the next transient arrived. However, a fault timeout,
with the accompanying shutdown of Q1, would occur if any of
the following test changes were made:
sistance, or
If any of these changes were made, the TIMER pin voltage
would not be able to decrease to zero during each transient
cycle, causing the pin’s voltage to repetitively increase with
the arrival of each transient. When the voltage at the TIMER
pin reached 4 volts, Q1 was shut off.
In an actual application, if transients are known to be very
frequent, the TIMER pin should be monitored on a scope dur-
ing testing of this proposed solution to see if the voltage stays
near zero, or if it drifts up a significant amount with the arrival
of each transient. If the TIMER pin voltage reaches 4V at any
time Q1 is shut off. The conditions required to cause a fault
timeout and a shutdown of Q1 are different for each applica-
tion.
- The upper voltage level at V
- The load current was increased by reducing the load re-
- The time interval between transients was decreased.
IN
held at its higher level for 20 ms, and at the
30119211
IN
was increased, or
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