LM5069_10 NSC [National Semiconductor], LM5069_10 Datasheet

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LM5069_10

Manufacturer Part Number
LM5069_10
Description
Output Voltage Clamping Using the LM5069 Hot Swap Controller
Manufacturer
NSC [National Semiconductor]
Datasheet
© 2010 National Semiconductor Corporation
Output Voltage Clamping
Using the LM5069 Hot Swap
Controller
The Issue
One of the many benefits of using the LM5069 Hot Swap
Controller, besides inrush current limiting and fault monitor-
ing, is that the controller supplies a voltage to the load that is
between defined limits. This feature prevents the load from
receiving a voltage less than what it is rated for (which could
result in erratic behavior), and prevents it from receiving a
voltage higher than what it is rated for, which could result in
overheating and/or damage. The voltage limits to the load are
set by the UVLO (Under-Voltage Lock Out) and OVLO (Over-
FIGURE 1. LM5069 Basic Application Circuit
301192
National Semiconductor
Application Note 2040
Dennis Morgan
March 15, 2010
Voltage Lock Out) thresholds, which are set with external
resistors (R1-R3 in Figure 1).
While the OVLO function can be used to keep excessive volt-
ages at V
back to this method of over-voltage protection is that the
voltage at V
condition. This can (and likely will) result in a shutdown of the
load circuitry, followed by a restart – an event which may in-
terrupt the normal operation of other associated circuitry.
IN
from reaching the load at V
OUT
is shut off for the duration of the over-voltage
30119201
OUT
, a potential draw-
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LM5069_10 Summary of contents

Page 1

Output Voltage Clamping Using the LM5069 Hot Swap Controller The Issue One of the many benefits of using the LM5069 Hot Swap Controller, besides inrush current limiting and fault monitor- ing, is that the controller supplies a voltage to the ...

Page 2

The Solution The solution presented here is to limit the voltage maximum value, rather than shut it off, when an over-volt- In normal operation (when the over-voltage condition is not present) the GATE pin of the LM5069 ...

Page 3

Test Results Two LM5069 circuits were tested with different value zener diodes for Z1. In both tests the pertinent external components were mohms 12.5 kohms PWR - Power Limit = 5 Watts ...

Page 4

Referring to Figure 4, initially V and V IN the GATE pin is at approximately 17.6V. The voltage at the TIMER pin is at zero since the load current is below the cur- rent limit threshold. When V increases quickly ...

Page 5

Trace 1: V (20V/div) OUT Trace 2: GATE pin (20V/div) Trace 3: TIMER pin (1V/div) Trace 4: V (20V/div) IN Referring to Figure 6, initially V and V IN GATE pin, which would normally be at 60V if Z1 were ...

Page 6

Power Dissipation in Q1 Implementing this voltage clamp requires re-evaluating the possible power dissipation in Q1. During an over-voltage con- dition where V is clamped, the power dissipated OUT due to the voltage difference across Q1 (V ...

Page 7

Notes 7 www.national.com ...

Page 8

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