STM804 STMICROELECTRONICS [STMicroelectronics], STM804 Datasheet - Page 9

• Manufacturer Part Number: STM804
• Description: 3V Supervisor with Battery Switchover
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

OPERATION
Reset Output
The STM690/704/795/802/804/805/806 Supervi-
sor asserts a reset signal to the MCU whenever
V
watchdog time-out occurs, or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM804/805)
for 0V < V
Without a back-up battery, RST is guaranteed val-
id down to V
During power-up, once V
threshold an internal timer keeps RST low for the
reset time-out period, t
returns high.
If V
low. Each time RST is asserted, it stays low for at
least the reset time-out period (t
goes below the reset threshold the internal timer
clears. The reset timer starts when V
above the reset threshold.
Push-button Reset Input (STM704/806)
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for t
36., page
has an internal 40k
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
V
Watchdog Input (NOT available on STM704/
795/806)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
reset is asserted. The internal watchdog timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting (see
37., page
CC
CC
CC
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (t
when not used.
goes below the reset threshold (V
drops below the reset threshold, RST goes
22) after it returns high. The MR input
23).
CC
CC
< V
=1V.
RST
pull-up resistor, allowing it to
if V
rec
. After this interval RST
BAT
CC
WD
WD
is greater than 1V.
exceeds the reset
rec
+ t
(1.6sec typ), the
). Any time V
rec
rec
).
(see
CC
RST
returns
Figure
Figure
), a
CC
Note: Input frequency greater than 20ns (50MHz)
will be filtered.
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through V
voltage V
SRAM to the back-up supply when V
Note: If back-up battery is not used, connect both
V
This family of Supervisors does not always con-
nect V
V
when V
is lower). This is done to allow the back-up battery
(e.g., a 3.6V lithium cell) to have a higher voltage
than V
Assuming that V
sures that battery back-up mode is entered before
V
to reliably retain data in most external SRAMs.
When V
oscillation around the V
ed to V
Note: The back-up battery may be removed while
V
pled (0.1µF typ), without danger of triggering a re-
set.
Table 4. I/O Status in Battery Back-up
Vccsw
BAT
BAT
OUT
CC
E
V
PFO
V
WDI
RST
RST
V
Pin
PFI
MR
CON
OUT
BAT
E
CC
is valid, assuming V
and V
connects to V
gets too close to the 2.0V minimum required
BAT
CC
CC
CC
CC
Connected to V
Disconnected from V
Disabled
Logic Low
High impedance
Logic High
Watchdog timer is disabled
Disabled
Logic Low
Logic High
Connected to V
Logic High (STM795)
.
BAT
OUT
to V
through a 3
STM690/704/795/802/804/805/806
is below V
OUT
recovers, hysteresis is used to avoid
, the devices automatically switch the
. With a backup battery installed with
OUT
to V
BAT
when V
CC
OUT
> 2.0V, switchover at V
SW
.
BAT
OUT
SO
(2.4V) or V
PMOS power switch.
BAT
(through a 100
Status
BAT
through internal switch
point. V
OUT
is adequately decou-
is greater than V
OUT
BAT
CC
(whichever
is connect-
falls.
switch)
SO
9/31
en-
CC
.