NCP1381 ONSEMI [ON Semiconductor], NCP1381 Datasheet - Page 7

• Manufacturer Part Number: NCP1381
• Description: Low−Standby High Performance PWM Controller
• Manufacturer: ONSEMI [ON Semiconductor]

Startup sequence
outlet, the NCP1381 starts to consume current. However,
due to a novel architecture, the internal startup current is
kept very low, below 15 mA as a maximum value. The
current delivered by the startup resistor also feeds the V
capacitor and its voltage rises. When the voltage on this
capacitor reaches the VCC
controller delivers pulses and increases its consumption. At
this time, the V
auxiliary supply is supposed to take over before V
collapses below VCC
arrangement of this structure:
Figure 4. The Timer Section Uses a Current Source
When the power supply is first connected to the mains
Confirmed
Figure 3. The Startup Resistor Brings V
Fault
UVLO
Soft−Burst
Soft−Start
Management
I
P
Flag
CC
to Charge Up the Capacitor
+
−
V
capacitor alone supplies the controller: the
CC
+
−
Above 15 V
Latchoff
OFF
+
+
4.0 V
VCC
VCC
. Figure 3 shows the internal
10
ON
ON
OFF
I
Reset
startup
level (typically 15 V), the
8
High Voltage
V
+
DD
CV
I
R
Auxiliary
total
Winding
I
SW
startup
timer
CC
I
V
CC3
4
CC
10
HV
+
CC
R
CV
C
startup
timer
http://onsemi.com
CC
CC
CC
NCP1381
7
delivered on Pin 9 and the auxiliary winding grows up the
V
SMPS is starting up), the controller smoothly pushes the
peak current to I
5 ms (typical internal soft−start period). After soft−start
completion, the peak current setpoint reaches its maximum
(during the startup period but also anytime a short−circuit
occurs), an internal error flag is asserted, I
that the system is pushed to the maximum power (I
maximum). This flag is used to detect a faulty condition,
where the converter asks for the maximum peak capability
longer than what has been programmed by the designer. The
duration of the faulty condition is actually set up by a
capacitor connected to Pin 4.
the fault comparator acknowledges for a problem, the
controller stops all driving pulses and turns−on the internal
I
phase creation, that is to say, forcing the V
despite the presence of the startup current still flowing via
the startup resistor. Therefore, I
I
of 7 V, I
up again. When V
If the fault is still there, pulses last either the timer duration
or are prematurely stopped if a VCC
sooner, and a new latchoff phase takes place. If the fault has
gone, the converter resumes operation. Figure 5 portrays the
waveforms obtained during a startup sequence followed by
a fault. One can see the action of the I
creates the latchoff phase and the various resets events on the
timer capacitor in presence of the soft−start end or an aborted
fault sequence.
capacitor needed to reach 4 V in a typical time period.
Suppose we would like a 100 ms fault duration, therefore:
C
CC3
total
timer
CC
As soon as V
Figure 4 shows a portion of this internal arrangement. If
Knowing that I
pin. Because the output voltage is below the target (the
to ensure proper operation. When V
current−source. This source serves for the latch−off
= 10 m x 100 m / 4 = 250 nF, select a 0.22 mF.
CC3
turns to zero and the startup current can lift V
CC
max
timer
reaches 15 V (VCC
CC
(0.8 V / R
reaches 15 V, a new attempt is made.
equals 10 mA, we can calculate the
sense
CC3
) which is reached after
should be greater than
ON
OFF
), driving pulses are
CC3
CC
condition occurs
P
CC
Flag, testifying
reaches a level
source which
to go down,
P
= I
CC
P