NCP1381 ONSEMI [ON Semiconductor], NCP1381 Datasheet - Page 11

• Manufacturer Part Number: NCP1381
• Description: Low−Standby High Performance PWM Controller
• Manufacturer: ONSEMI [ON Semiconductor]

Figure 10. Core Reset Detection is Done Through the
−1.00
7.00
5.00
3.00
1.00
Monitoring of a Dedicated Auxiliary Winding
Possible
Restart
Demag
0 V
V
DD
2
V
DD
D
CLK
+
R
S
Q
Q
DRV
+
−
Figure 9. Internal QR Architecture
Fault
45 mV
http://onsemi.com
+
45 mV
NCP1381
V
DD
−
+
11
Shot
One
V
DD
Skipping Cycle Mode
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 6 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 11) and
follows the following formula:
with
L
F
I
D
+
P
sw
P
burst
The NCP1381 automatically skips switching cycles when
= Peak Current at which Skip Cycle Occurs
Prioritary
= Primary Inductance
Reset
= Switching Frequency Within the Burst
Blanking
+
−
= Burst Width/Burst Recurrence
+
1
2
3 ms
@ L P @ I P
+
−
Reset Reset
D
Skip
CLK
2
S
R
@ F sw @ D burst
I
Limit
Q
Q
DRV
DRV
(eq. 1)