NCP1280_05 ONSEMI [ON Semiconductor], NCP1280_05 Datasheet - Page 16

• Manufacturer Part Number: NCP1280_05
• Description: Active Clamp Voltage Mode PWM Controller for Off-Line Applications
• Manufacturer: ONSEMI [ON Semiconductor]

7 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are re−enabled,
the converter will eventually reach regulation exhibiting a
non−monotonic startup behavior. But, if the converter
output is completely discharged when the outputs are
re−enabled, the cycle may repeat and the converter will not
start.
capacitor is discharged. Once the fault is removed, a
soft−start cycle commences. The soft−start steady state
voltage is approximately 4.1 V.
Control Outputs
and OUT2, with adjustable overlap delay (t
precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.
Oscillator
Ramp
OUT2
OUT1
If the soft−start period is too long, V
In the event of an UV, OV, or cycle skip fault, the soft−start
The NCP1280 has two in−phase control outputs, OUT1
Figure 35. Control Outputs Timing Diagram
t
D
(Leading)
Figure 34. Soft−Start Timing Diagram
OUT1
OUT2
t
D
(Trailing)
AUX
will discharge to
D
). OUT2
http://onsemi.com
V
SS
NCP1280
16
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.
disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and V
reaches 11 V again.
can supply up to 10 mA each and their high state voltage is
usually 0.2 V below V
voltage should not exceed the maximum input voltage of the
driver stage.
a driver should be used between the NCP1280 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.
Time Delay
a resistor (R
overlap delay of 80 ns is obtained when R
is not present, the delay is 200 ns.
selecting appropriate values of R
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
maximum overlap delay, t
duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.
Generally, OUT1 controls the main switching element.
Once V
The control outputs are biased from V
If the control outputs need to drive a large capacitive load,
The overlap delay between the outputs is set connecting
The output duty cycle can be adjusted from 0% to 85%
For example, if the converter operates at a frequency of
AUX
D
) between the t
reaches 11 V, the internal startup circuit is
t D(max) v
AUX
D(max)
. Therefore, the auxiliary supply
D
(1 * DC)
and V
, depends on the maximum
FF
2
and V
REF
AUX
pins. A minimum
D
DC(inv)
is 60 kW. If R
. The outputs
. It should
AUX
D