ICE3DS01L_05 INFINEON [Infineon Technologies AG], ICE3DS01L_05 Datasheet - Page 11

• Manufacturer Part Number: ICE3DS01L_05
• Description: Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell
• Manufacturer: INFINEON [Infineon Technologies AG]

3.5
Figure 10
There is a cycle by cycle Current Limiting realized by the
Current-Limit comparator C10 to provide an overcurrent
detection. The source current of the external Power Switch is
sensed via an external sense resistor R
R
V
exceeds the internal threshold voltage V
C10 immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation is
added to support the immediate shut down without delay of
the Power Switch in case of Current Limiting. The influence
of the AC input voltage on the maximum output power can
thereby be avoided.
To prevent the Current Limiting from distortions caused by
leading edge spikes a Leading Edge Blanking is integrated in
the current sense path for the comparators C10, C12 and the
PWM-OP.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a short
winding in the transformer or the secondary diode is shorten.
To ensure that there is no accidentally entering of the
Latched Mode by the comparator C11 a spike blanking with
190ns is integrated in the output path of comparator C11.
The output of comparator C12 is activated by the Gate G10
if Active Burst Mode is entered. Once activated the current
limiting is thereby reduced to 0.257V. This voltage level
Version 2.1
PWM Latch
Sense
Sense
FF1
PWM-OP
which is fed into the pin CS. If the voltage V
the source current is transformed to a sense voltage
Active Burst
Mode
G10
Current Limiting
&
Latched Off
Current Limiting
Propagation-Delay
Mode
Compensation
CS
Blanking
C10
C12
190ns
Spike
10kΩ
0.257V
V
D1
csth
C11
Sense
csth
Current Limiting
the comparator
Blanking
. By means of
Leading
220ns
Edge
1pF
1.66V
Sense
11
determines the power level when the Active Burst Mode is
left if there is a higher power demand.
3.5.1
Figure 11
Each time when the external Power Switch is switched on a
leading edge spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse recovery
time. To avoid a premature termination of the switching
pulse this spike is blanked out with a time constant of t
220ns. During that time there can’t be an accidentally switch
off of the gate drive.
3.5.2
In case of overcurrent detection the shut down of the external
Power Switch is delayed due to the propagation delay of the
circuit. This delay causes an overshoot of the peak current
I
(see Figure 12).
Figure 12
The overshoot of Signal2 is bigger than of Signal1 due to the
steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation Delay
Compensation is integrated to limit the overshoot
dependency on dI/dt of the rising primary current. That
means the propagation delay time between exceeding the
current sense threshold V
external Power Switch is compensated over temperature
peak
I
I
I
peak2
peak1
Limit
V
csth
which depends on the ratio of dI/dt of the peak current
I
V
Sense
Sense
Propagation Delay Compensation
Leading Edge Blanking
Leading Edge Blanking
Current Limiting
I
Overshoot2
Signal2
csth
t
Functional Description
LEB
= 220ns
and the switch off of the
ICE3DS01L/LG
Signal1
t
Propagation Delay
15 Nov 2005
I
Overshoot1
t
LEB
F3
t
=