M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 26

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR032FT, M58WR032FB
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will per-
form. Refer to
on read operations.
The Configuration Register is set through the
Command Interface. After a Reset or Power-Up
the device is configured for asynchronous page
read (CR15 = 1). The Configuration Register bits
are described in
tion of the burst length, burst type, burst X latency
and the Read operation. Refer to Figures
for examples of synchronous burst configurations.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch be-
tween asynchronous and synchronous Bus Read
operations. When the Read Select bit is set to ’1’,
read operations are asynchronous; when the
Read Select bit is set to ’0’, read operations are
synchronous. Synchronous Burst Read is support-
ed in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available. For correct operation the
X-Latency bits can only assume the values in
ble 9., Configuration
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied:
1. Depending on whether t
2. and also
where
n is the chosen X-Latency configuration code
t
t
Low, whichever occurs last
t
whichever occurs last
t
system CPU,
t
t
26/86
K
AVK_CPU
DELAY
QVK_CPU
KQV
ACC
is the clock period
supplied either one of the following two
equations must be satisfied:
is the clock to data valid time
is the random access time of the device.
is address valid, L Low, or E Low to clock,
(n + 1) t
(n + 2) t
t
K
is clock to address valid, L Low, or E
is the data setup time required by the
> t
KQV
READ MODES
K
K
Table 9.
+ t
t
t
ACC
ACC
QVK_CPU
Register.
- t
+ t
They specify the selec-
AVK_CPU
DELAY
AVK_CPU
section for details
+ t
+ t
QVK_CPU
or t
QVK_CPU
DELAY
6
and
Ta-
is
7
Refer to
Configuration
Wait Polarity Bit (CR10)
In synchronous burst mode the Wait signal indi-
cates whether the output data are valid or a WAIT
state must be inserted. The Wait Polarity bit is
used to set the polarity of the Wait signal. When
the Wait Polarity bit is set to ‘0’ the Wait signal is
active Low. When the Wait Polarity bit is set to ‘1’
the Wait signal is active High (default).
Data Output Configuration Bit (CR9)
The Data Output Configuration bit determines
whether the output remains valid for one or two
clock cycles. When the Data Output Configuration
Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the
output data is valid for two clock cycles.
The Data Output Configuration depends on the
condition:
where t
setup time required by the system CPU and t
is the clock to data valid time. If this condition is not
satisfied, the Data Output Configuration bit should
be set to ‘1’ (two clock cycles). Refer to
X-Latency and Data Output Configuration Exam-
ple.
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the
Wait output pin, WAIT. When WAIT is asserted,
Data is Not Valid and when WAIT is deasserted,
Data is Valid. When the Wait bit is ’0’ the Wait out-
put pin is asserted during the wait state. When the
Wait bit is ’1’ (default) the Wait output pin is assert-
ed one clock cycle before the wait state.
Burst Type Bit (CR7)
The Burst Type bit is used to configure the se-
quence of addresses read as sequential or inter-
leaved. When the Burst Type bit is ’0’ the memory
outputs from interleaved addresses; when the
Burst Type bit is ’1’ (default) the memory outputs
from sequential addresses. See
Type
output from a given starting address in each mode.
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during Syn-
chronous Burst Read operations. When the Valid
Clock Edge bit is ’0’ the falling edge of the Clock is
the active edge; when the Valid Clock Edge bit is
’1’ the rising edge of the Clock is active.
Wrap Burst Bit (CR3)
The burst reads can be confined inside the 4 or 8
Word boundary (wrap) or overcome the boundary
t
K
Definition, for the sequence of addresses
> t
K
KQV
is the clock period, t
Figure 6., X-Latency and Data Output
+ t
Example.
QVK_CPU
QVK_CPU
Table 10., Burst
is the data
Figure 6.,
KQV