HYB18T512160BF QIMONDA [Qimonda AG], HYB18T512160BF Datasheet - Page 26

• Manufacturer Part Number: HYB18T512160BF
• Description: 200 Pin Small-Outlined DDR2 SDRAMs Modules
• Manufacturer: QIMONDA [Qimonda AG]

Rev. 1.1, 2006-10
03292006-5LTN-QML0
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data
strobe)
DQS falling edge hold time from CK (write
cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
QH
QHS
(base)
(base)
(base)
(base)
(base)
(base)
26
DDR2–533
–500
2
0.45
3
0.45
WR +
t
225
–25
0.35
–450
0.35
—
– 0.25
100
–25
0.2
0.2
MIN. (
—
375
0.6
250
2 ×
t
2
0
t
—
Min.
IS
AC.MIN
HP
+
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
–
t
t
AC.MIN
t
CK
QHS
t
t
CL,
RP
+
t
t
CH
IH
)
Max.
+500
—
0.55
—
0.55
—
––
––
—
—
+450
—
300
+ 0.25
—
—
—
—
t
—
—
—
t
t
—
12
—
400
AC.MAX
AC.MAX
AC.MAX
SO-DIMM DDR2 SDRAM Module
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
—
ps
ps
t
ps
ps
ps
t
ns
—
ps
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 18
Note
6)7)
8)18)
9)
10)
11)
11)
11)
11)
12)
13)
11)
11)
14)
14)
1)2)3)4)5)