HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 68

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 53
3.24.2
The Self-Refresh command can be used to retain data,
even if the rest of the system is powered down. When
in the Self-Refresh mode, the DDR2 SDRAM retains
data without external clocking. The DDR2 SDRAM
device has a built-in timer to accommodate Self-
Refresh operation. The Self-Refresh Command is
defined by having CS, RAS, CAS and CKE held LOW
with WE HIGH at the rising edge of the clock. The
device must be in idle state and ODT must be turned off
before issuing Self Refresh command, by either driving
ODT pin LOW or using EMRS(1) command. Once the
command is registered, CKE must be held LOW to
keep the device in Self-Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and
is automatically enabled upon exiting Self Refresh.
When the DDR2 SDRAM has entered Self-Refresh
mode all of the external control signals, except CKE,
are “don’t care”. The DRAM initiates a minimum of one
Auto Refresh command internally within
once it enters Self Refresh mode. The clock is internally
disabled during Self-Refresh Operation to save power.
The minimum time that the DDR2 SDRAM must remain
in Self Refresh mode is
external clock frequency or halt the external clock one
Data Sheet
CMD
CKE
CK, CK
P re ch a rg e
T0
"high"
Auto Refresh Timing
Self-Refresh Command
T1
N O P
> = t
t
CKE
. The user may change the
R P
T2
N O P
R E F R E S H
T3
A U T O
t
CKE
> = t
period
R F C
N O P
68
clock after Self-Refresh entry is registered, however,
the clock must be restarted and stable before the
device can exit Self-Refresh operation.
The procedure for exiting Self Refresh requires a
sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self-Refresh Exit
command is registered, a delay of at least
be satisfied before a valid command can be issued to
the device to allow for any internal refresh in progress.
CKE must remain HIGH for the entire Self-Refresh exit
period
Refresh, the DDR2 SDRAM can be put back into Self
Refresh mode after
commands must be registered on each positive clock
edge during the Self-Refresh exit interval
should be turned off during
The use of Self Refresh mode introduces the possibility
that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode.
Upon exit from Self Refresh, the DDR2 SDRAM
requires a minimum of one extra auto refresh command
before it is put back into Self Refresh Mode.
R E F R E S H
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
A U T O
t
XSRD
for proper operation. Upon exit from Self
N O P
t
XSNR
> = t
512-Mbit DDR2 SDRAM
t
expires. NOP or deselect
XSNR
R F C
N O P
Functional Description
09112003-SDM9-IQ3P
.
Rev. 1.3, 2005-01
A N Y
t
t
XSNR
XSNR
AR
. ODT
must