CY14E256L-D45I CYPRESS [Cypress Semiconductor], CY14E256L-D45I Datasheet - Page 2

• Manufacturer Part Number: CY14E256L-D45I
• Description: 256 Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Configurations
Table 1. Pin Definitions
Document Number: 001-06968 Rev. *G
Pin Name
DQ
A
V
HSB
0
V
V
WE
CE
OE
0
–A
CAP
SS
CC
-DQ
14
7
Alt
W
G
E
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
I/O Type
Ground
Input
Input
Input
Input
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
Figure 1. Pin Diagram: 32-Pin SOIC/DIP
Description
CY14E256L
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