CY14E256L-D45I CYPRESS [Cypress Semiconductor], CY14E256L-D45I Datasheet - Page 12

no-image

CY14E256L-D45I

Manufacturer Part Number
CY14E256L-D45I
Description
256 Kbit (32K x 8) nvSRAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Switching Waveforms
Document Number: 001-06968 Rev. *G
t
t
t
t
t
Notes
RC
SA
CW
HACE
RECALL
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Parameter
[18, 19]
[16]
[18, 19]
ADDRESS
DQ (DATA)
[18, 19]
CE
OE
t
t
t
t
AVAV
AVEL
ELEH
ELAX
Alt
t
SA
A
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
D
DATA VALID
D
Figure 12. CE Controlled Software STORE/RECALL Cycle
R
t
t
SCE
RC
E
S
t
HACE
S
#
1
Description
[19]
Min
25
20
20
0
A
D
25 ns
D
t
R
RC
E
S
Max
DATA VALID
20
S
#
6
Min
35
25
20
t
0
STORE
[19]
35 ns
HIGH IMPEDANCE
/ t
Max
20
RECALL
Min
45
30
20
0
CY14E256L
45 ns
Page 12 of 18
Max
20
Unit
ns
ns
ns
ns
μs
[+] Feedback

Related parts for CY14E256L-D45I