CY14E256L-SZ45XCT Cypress Semiconductor Corp, CY14E256L-SZ45XCT Datasheet
CY14E256L-SZ45XCT
Specifications of CY14E256L-SZ45XCT
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CY14E256L-SZ45XCT Summary of contents
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... Document Number: 001-06968 Rev. *H 256 Kbit (32K x 8) nvSRAM Functional Description The Cypress CY14E256L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell ...
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... SRAM Read Cycle .........................................................10 SRAM Write Cycle ..........................................................11 AutoStore or Power Up RECALL .......................................12 Software Controlled STORE/RECALL Cycle .....................13 Switching Waveforms .........................................................14 Part Numbering Nomenclature (Commercial and Industrial) ...............................................15 Ordering Information ...........................................................15 Document History Page ......................................................18 Sales, Solutions, and Legal Information ...........................19 Worldwide Sales and Design Support ............................19 Products .........................................................................19 CY14E256L Page [+] Feedback [+] Feedback ...
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... V Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM CAP to nonvolatile elements. Document Number: 001-06968 Rev. *H Figure 1. Pin Diagram: 32-Pin SOIC/DIP Description CY14E256L Page [+] Feedback [+] Feedback ...
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... Device Operation The CY14E256L nvSRAM is made up of two functional compo- nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation) ...
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... RESET once again exceeds the sense voltage of V cycle is automatically initiated and takes t Document Number: 001-06968 Rev the CY14E256L WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation Kohm resistor is connected either between WE and system V CC ...
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... STORE, the WRITE is inhibited until a negative transition detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The CY14E256L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between V and V using leads and traces that are as short ...
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... CE and OE LOW and WE HIGH for output behavior. 4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 5. While there are 15 addresses on the CY14E256L, only the lower 14 are used to control software modes. Document Number: 001-06968 Rev. *H manufacturing test to ensure these system routines work consistently ...
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... Inputs are static MHz ns, CE > ns, CE > ns, CE > Max, V < V < Max, V < V < > that is where the power supply connection is made CY14E256L Ambient Temperature V CC 0°C to +70°C 4.5V to 5.5V -40°C to +85°C 4.5V to 5.5V Min Max Unit Commercial Industrial 100 – 0.2V). 1.5 ...
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... MHz 3.0V CC [8] Test Conditions Test conditions follow standard test methods and proce- dures for measuring thermal impedance, per EIA / JESD51. Figure 6. AC Test Loads 5.0V Output 512Ω CY14E256L Min Max Unit 2.4 V 0 260 uF Min Unit ...
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... Figure 8. SRAM Read Cycle 2: CE and OE Controlled Notes 9. WE and HSB must be HIGH during SRAM Read cycles. 10. Device is continuously selected with CE and OE both Low. 11. Measured ±200 mV from steady state output voltage. Document Number: 001-06968 Rev Description Min Max CY14E256L Unit Min Max Min Max ...
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... HSB must be high during SRAM WRITE cycles. 14 must be greater than V during address transitions. IH Document Number: 001-06968 Rev Description Min SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE SCE PWE t SD DATA VALID HIGH IMPEDANCE CY14E256L Max Min Max Min Max [13, 14 LZWE [13, 14 Page Unit ns ...
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... Document Number: 001-06968 Rev. *H Description Rise Time HSB low SWITCH Figure 11. AutoStore/Power Up RECALL . SWITCH . If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store SWITCH CY14E256L CY14E256L Unit Min Max μs 550 10 ms μs 1 4.0 4 ...
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... The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence). 19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. Document Number: 001-06968 Rev. *H [19 Description Min Max DATA VALID CY14E256L Unit Min Max Min Max [19 ...
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... Hardware STORE Pulse Width PHSB HLHX t Hardware STORE Low to STORE Busy HLBL Switching Waveforms Note 20 only applicable after t is complete. DHSB STORE Document Number: 001-06968 Rev. *H Description Figure 13. Hardware STORE Cycle CY14E256L CY14E256L Unit Min Max 700 300 ns Page [+] Feedback [+] Feedback ...
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... CY14E256L-SZ25XCT CY14E256L-SZ25XC CY14E256L-SZ25XIT CY14E256L-SZ25XI 35 CY14E256L-SZ35XCT CY14E256L-SZ35XC CY14E256L-SZ35XIT CY14E256L-SZ35XI 45 CY14E256L-SZ45XCT CY14E256L-SZ45XC CY14E256L-SZ45XIT CY14E256L-SZ45XI CY14E256L-D45I This table contains Final information. Contact your local Cypress sales representative for availability of these parts Document Number: 001-06968 Rev. *H Option Tape & Reel Blank - Std. Temperature Commercial (0 to 70° Industrial (-40 to 85° ...
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... Figure 14. 32-Pin (300 Mil) SOIC (51-85127) PIN DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] REFERENCE JEDEC MO-119 0.405[10.287] 0.419[10.642] 32 SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] CY14E256L MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 51-85058 *A 0.006[0.152] 0.021[0.533] 0.012[0.304] 0.041[1.041] 51-85127-*A Page [+] Feedback [+] Feedback ...
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... Package Diagram (continued) Document Number: 001-06968 Rev. *H Figure 15. 32-Pin (300 Mil) CDIP (001-51694) CY14E256L 001-51694 ** Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY14E256L 256 Kbit (32K x 8) nvSRAM Document Number: 001-06968 Submission Rev. ECN No. Date ** 427789 See ECN *A 437321 See ECN *B 472053 See ECN *C 503290 See ECN *D 1349963 See ECN *E 2427986 See ECN *F 2606744 02/19/09 *G 2708327 05/18/2009 *H 2815609 11/26/2009 Document Number: 001-06968 Rev ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06968 Rev. *H All products and company names mentioned in this document may be the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised November 26, 2009 CY14E256L Page [+] Feedback [+] Feedback ...