CY14E064L-SZ25XC CYPRESS [Cypress Semiconductor], CY14E064L-SZ25XC Datasheet - Page 5

• Manufacturer Part Number: CY14E064L-SZ25XC
• Description: 64 Kbit (8K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

chip is disabled. It is important that READ cycles and not WRITE
cycles are used in the sequence. It is not necessary that OE is
LOW for a valid sequence. After the t
the SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the non-volatile information is transferred
into the SRAM cells. After the t
once again ready for READ and WRITE operations. The
RECALL operation does not alter the data in the non-volatile
elements.
Data Protection
The CY14E064L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The CY14E064L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Document Number: 001-06543 Rev. *D
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
CC
is less than V
CC
and V
SS,
using leads and traces that are as short
SWITCH
. If the CY14E064L is in a WRITE
RECALL
STORE
cycle time, the SRAM is
cycle time is fulfilled,
Low Average Active Power
CMOS technology provides the CY14E064L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14E064L depends on the
following items:
Figure 3. Current Versus Cycle Time (READ)
Figure 4. Current Versus Cycle Time (WRITE)
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The V
7. IO loading
CC
level
Figure 3
shows the relationship between I
CY14E064L
Page 5 of 17
CC
and
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