HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 25

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

prior to the WRITE command, as shown in
a write mask: when asserted HIGH, input data will be masked and no write will be performed.
Figure 21
2.4.5.5
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in
The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE
command, a subsequent ACTIVE command to the same bank cannot be issued until t
part of the row precharge time is hidden during the access of the last data elements.
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same READ burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
Data Sheet
READ to WRITE Timing
READ to PRECHARGE
Figure
21. With the registration of the WRITE command, DQM acts as
Figure
25
22.
Functional DescriptionCommands
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
RP
is met. Please note that
05282004-NZNK-8T0D
Rev. 1.71, 2007-01