HYB314400BJ-50- SIEMENS [Siemens Semiconductor Group], HYB314400BJ-50- Datasheet - Page 10

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HYB314400BJ-50-

Manufacturer Part Number
HYB314400BJ-50-
Description
1M x 4-Bit Dynamic RAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
Notes
1. All voltages are referenced to
2.
3.
4. Address can be changed once or less while RAS =
5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least
6. AC measurements assume
7.
8. Measured with a load equivalent to 100 pF and at
9. Operation within the
10.Operation within the
11.Either
12.
13.Either
14.Either
15.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
Semiconductor Group
I
I
or less during a fast page mode cycle (
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
V
are also measured between
(
a reference point only: If
controlled by
a reference point only: If
controlled by
and are not referenced to output voltage levels.
data sheet as electrical characteristics only. If
and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if
t
write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets
of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
leading edge in read-write cycles.
t
t
I
RWD
CC1
CC1
OFF (MAX.)
WCS
IH (MIN.)
OL
,
= 2 mA).
and
,
I
t
CC3
RWD
t
t
t
t
RCH
DZC
CDD
RWD (MIN.)
and
I
,
CC4
and
,
I
CC4
t
or
or
or
CWD
V
depend on output loading. Specified values are measured with the output open.
t
t
t
CAC
AA
t
t
IL (MAX.)
DZO
and
RRH
ODD
t
,
OEZ (MAX.)
,
.
t
.
AWD
t
CWD
must be satisfied.
must be satisfied for a read cycle.
must be satisfied.
I
CC6
t
t
are reference levels for measuring timing of input signals. Transition times
and
RCD (MAX.)
RAD (MAX.)
depend on cycle rate.
t
define the time at which the outputs achieve the open-circuit condition
CWD (MIN.)
t
t
t
RCD
CPWD
RAD
t
V
T
V
IH
= 5 ns.
is greater than the specified
limit ensures that
is greater than the specified
limit ensures that
are not restrictive operating parameters. They are included in the
SS
and
,
.
t
AWD
V
IL
t
.
PC
t
).
AWD (MIN.)
10
t
WCS
t
t
RAC (MAX.)
RAC (MAX.)
V
and
IL
. In the case of
t
WCS (MIN.)
V
t
OH
CPWD
can be met.
can be met.
= 2.0 V (
t
t
RCD (MAX.)
RAD (MAX.)
, the cycle is an early write cycle
t
CPWD (MIN.)
HYB 314400BJ-50/-60
I
I
CC4
OH
3.3 V 1M
limit, then access time is
limit, then access time is
t
t
RCD (MAX.)
RAD (MAX.)
it can be changed once
= – 2 mA),
, the cycle is a read-
is specified as
is specified as
1998-10-01
V
4 DRAM
OL
= 0.8 V

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