CY62127DV18L-55BVI CYPRESS [Cypress Semiconductor], CY62127DV18L-55BVI Datasheet - Page 5

• Manufacturer Part Number: CY62127DV18L-55BVI
• Description: 1 Mb (64K x 16) Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Document #:38-05226 Rev.*A
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. If both byte enables are toggled together, this value is 10 ns.
11. t
12. The internal Write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
8.
9.
Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading
of the specified IOL/IOH and 50 pF load capacitance.
At any given temperature and voltage condition, t
HZOE
[10]
Parameter
, t
HZCE
[12]
, t
HZBE
, and t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-up
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
transitions are measured when the outputs enter a high-impedance state.
(Over the Operating Range)
[9]
[9]
HZCE
[9,11]
[9,11]
[9]
[9,11]
Description
is less than t
[9]
PRELIMINARY
[9,11]
LZCE
, t
HZBE
[8]
IL
is less than t
, BHE and/or BLE = V
LZBE
, t
HZOE
IL
. All signal
is less than t
Min.
CY62127DV18-55
55
10
10
55
40
40
40
40
25
10
5
5
0
0
0
0
CY62127DV18
Max.
55
55
25
20
20
55
55
20
20
MoBL2
Page 5 of 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®