M24128-BRBN6 STMICROELECTRONICS [STMicroelectronics], M24128-BRBN6 Datasheet - Page 8

• Manufacturer Part Number: M24128-BRBN6
• Description: 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the R/W bit (RW) reset
to 0. The device acknowledges this, as shown in
Figure
vice responds to each address byte with an ac-
knowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte
ble
cant Byte
address of the byte in memory.
8/25
4.) is sent first, followed by the Least Signifi-
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
7., and waits for two address bytes. The de-
(Table
5.). Bits b15 to b0 form the
NO ACK
DEV SEL
DEV SEL
Figure
DATA IN N
R/W
R/W
ACK
ACK
6..
NO ACK
BYTE ADDR
BYTE ADDR
(Ta-
ACK
ACK
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay t
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
BYTE ADDR
BYTE ADDR
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
DATA IN 2
AI01120C
W
, and the suc-
th
bit” time