M24128-BRBN6 STMICROELECTRONICS [STMicroelectronics], M24128-BRBN6 Datasheet - Page 10

• Manufacturer Part Number: M24128-BRBN6
• Description: 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 8. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
14.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in
10/25
and
First byte of instruction
with RW = 0 already
decoded by the device
Table
15., but the typical time is shorter.
ReSTART
STOP
Figure
w
NO
) is shown in
NO
8., is:
START Condition
DEVICE SELECT
WRITE Cycle
Addressing the
with RW = 0
Operation is
in Progress
Returned
Memory
ACK
Next
YES
Table
WRITE Operation
WRITE Operation
DATA for the
Continue the
YES
NO
–
–
–
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
and Receive ACK
Send Address
Condition
START
Random READ Operation
DEVICE SELECT
Continue the
with RW = 1
YES
AI01847C