M24128-BRBN6 STMICROELECTRONICS [STMicroelectronics], M24128-BRBN6 Datasheet - Page 4

• Manufacturer Part Number: M24128-BRBN6
• Description: 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24128-BW, M24128-BR, M24256-BW, M24256-BR
SUMMARY DESCRIPTION
These I
grammable memory (EEPROM) devices are orga-
nized as 32K x 8 bits (M24256-BW and M24256-
BR) and 16K x 8 bits (M24128-BW and M24128-
BR).
Figure 2. Logic Diagram
Table 2. Signal Names
I
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
The device behaves as a slave in the I
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
4/25
2
C uses a two-wire serial interface, comprising a
E0, E1, E2
SDA
SCL
WC
V
V
CC
SS
E0-E2
SCL
2
WC
C-compatible electrically erasable pro-
3
V CC
V SS
M24256-B
M24128-B
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
2
C bus definition.
2
C protocol,
SDA
AI02809
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset
In order to prevent inadvertent Write operations
during Power Up, a Power On Reset (POR) circuit
is implemented.
At Power Up, the device will not respond to any in-
struction until V
voltage (this threshold is lower than the V
mum operating voltage defined in
ble
from the normal operating voltage, below the POR
threshold voltage, all the operations are disabled
and the device will not respond to any instruction.
Prior to selecting and issuing instructions to the
memory, a valid and stable V
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (t
Figure 3. DIP, SO and TSSOP Connections
Note: See
9.). In the same way, as soon as V
sions, and how to identify pin-1.
PACKAGE MECHANICAL
Table
V SS
CC
E0
E1
E2
3.), terminated by an acknowl-
has reached the POR threshold
M24256-B
M24128-B
1
2
3
4
W
AI02810B
).
8
7
6
5
section for package dimen-
CC
V CC
WC
SCL
SDA
Table 8.
voltage must be
th
CC
bit time,
CC
and
drops
mini-
Ta-