M95320-BN1T STMICROELECTRONICS [STMicroelectronics], M95320-BN1T Datasheet - Page 13
M95320-BN1T
Manufacturer Part Number
M95320-BN1T
Description
64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M95320-BN1T.pdf
(39 pages)
- Current page: 13 of 39
- Download datasheet (550Kb)
Figure 10. Write Disable (WRDI) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 10, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
S
C
D
Q
High Impedance
0
1
2
Instruction
3
4
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
– Power-up
– WRDI instruction execution
– WRSR instruction completion
– WRITE instruction completion.
5
6
7
AI03750D
M95640, M95320
13/39
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