M95320-WMN6P STMicroelectronics, M95320-WMN6P Datasheet
M95320-WMN6P
Specifications of M95320-WMN6P
M95320-WMN6P
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M95320-WMN6P Summary of contents
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... Features ■ Compatible with SPI bus serial interface (positive clock SPI modes) ■ Single supply voltage: – 4.5 to 5.5 V for M95320 – 2.5 to 5.5 V for M95320-W – 1.8 to 5.5 V for M95320-R ■ 10 MHz, 5 MHz or 2 MHz clock rates ■ write time ■ ...
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... Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R ...
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... M95320, M95320-W, M95320-R 6.3.2 6.3.3 6.3.4 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering ...
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... AC measurement conditions Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 13. DC characteristics (M95320, device grade 3 Table 14. DC characteristics (M95320-W, device grade Table 15. DC characteristics (M95320-W, device grade Table 16. DC characteristics (M95320- Table 17. AC characteristics (M95320, device grade Table 18. AC characteristics (M95320-W, device grade Table 19. AC characteristics (M95320-W, device grade Table 20 ...
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... M95320, M95320-W, M95320-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 ...
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... Description 1 Description The M95320, M95320-W and M95320-R are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high-speed SPI-compatible bus. The devices are 32 Kbit devices organized as 4096 × 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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... M95320, M95320-W, M95320-R Table 1. Signal names Signal name HOLD Description Serial Clock Serial data input Serial data output Chip Select Write Protect Hold Supply voltage Ground Doc ID 5711 Rev 12 Description 7/44 ...
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... Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/44 must be held stable and within the specified valid range: CC Table 13 to Table 16). These signals are described next. Doc ID 5711 Rev 12 M95320, M95320-W, M95320 ...
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... M95320, M95320-W, M95320-R 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write operations. ...
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... R SDO SDI SCK SPI memory R R device S W HOLD Figure 3) ensures that a device is not selected if the requirement is met. The typical value 100 k. SHCH Doc ID 5711 Rev 12 M95320, M95320-W, M95320 SPI memory SPI memory R device device HOLD ...
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... M95320, M95320-W, M95320-R 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C) ...
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... RES (min), V (max)] range defined continuously rises from V CC Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs. Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R CC Table 8, Table reaches a valid and stable V CC Table 8, Table During this SS CC voltage ...
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... M95320, M95320-W, M95320-R 4.1.4 Power-down During power-down (continuous decrease in the V V operating voltage defined in CC ● deselected (Chip Select S should be allowed to follow the voltage applied on V ● in Standby Power mode (there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode ...
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... Write-protected block size Status Register bits BP1 14/44 Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R for a Array addresses protected 32 Kbit devices none 0C00h - 0FFFh 0800h - 0FFFh 0000h - 0FFFh ...
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... M95320, M95320-W, M95320-R 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD Address Register Figure 6. High Voltage Control Logic I/O Shift Register and Counter Doc ID 5711 Rev 12 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only ...
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... Read from Memory Array Write to Memory Array 7, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R Table 3. Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 ...
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... M95320, M95320-W, M95320-R 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high ...
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... SRWD Status Register Write Protect 18/44 Table 4 and the status and control bits of the Status Table 4) becomes protected against Write Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R Figure 9. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit b0 WIP ...
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... M95320, M95320-W, M95320-R Figure 9. Read Status Register (RDSR) sequence 6.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, sending the instruction code followed by the data byte on Serial Data input (D), and driving the Chip Select (S) signal high ...
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... Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status Register, can be used. Table 6. Address range bits Device Address bits 1. b15 to b12 are Don’t Care. 20/44 M95320, M95320-W, M95320-R Protected area Write Protected Write Protected Table (1) 32 Kbit devices A11-A0 ...
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... M95320, M95320-W, M95320-R Figure 10. Write Status Register (WRSR) sequence 6.5 Read from Memory Array (READ) As shown in Figure low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q) ...
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... Write in Progress (WIP) bit is reset is internally executed as a sequence of two consecutive Instruction 16-Bit Address High Impedance Table 6, the most significant address bits are Don’t Care. Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R Figure 13, the next byte Data Byte ( ...
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... M95320, M95320-W, M95320-R Figure 13. Page Write (WRITE) sequence Depending on the memory size, as shown Instruction 16-Bit Address Data Byte 2 Data Byte Table 6, the most significant address bits are Don’t Care. Doc ID 5711 Rev Data Byte Data Byte Instructions AI01796D 23/44 ...
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... Initial delivery state The device is delivered with the memory array set to all 1s (each byte = FFh). The Status register write disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0. 24/44 M95320, M95320-W, M95320-R Doc ID 5711 Rev 12 ...
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... M95320, M95320-W, M95320-R 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Symbol C Load capacitance L Input rise and fall times Input pulse voltages Input and output timing reference voltages 1. Output Hi-Z is defined as the point where data out is no longer driven. 26/44 M95320, M95320-W, M95320-R Parameter Parameter Parameter (1) Parameter Doc ID 5711 Rev 12 Min. Max. ...
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... Figure 14. AC measurement I/O waveform Table 12. Capacitance Symbol C Output capacitance (Q) OUT C Input capacitance (D) IN Input capacitance (other pins) 1. Sampled only, not 100% tested. Table 13. DC characteristics (M95320, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current ...
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... DC and AC parameters Table 14. DC characteristics (M95320-W, device grade 6) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current I CC1 (Standby) V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage OH Internal reset threshold ...
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... M95320, M95320-W, M95320-R Table 16. DC characteristics (M95320-R) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CCR I Supply current (Standby) CC1 V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage OH Internal reset threshold ...
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... DC and AC parameters Table 17. AC characteristics (M95320, device grade 3) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time CHSL ...
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... M95320, M95320-W, M95320-R Table 18. AC characteristics (M95320-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS ( CLQV CLQX HO (2) ...
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... DC and AC parameters Table 19. AC characteristics (M95320-W, device grade 3) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time CHSL ...
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... HHQV LZ ( HLQZ the application uses the M95320-R device with 2.5 V V refer to Table 18: AC characteristics (M95320-W, device grade must never be lower than the shortest possible clock period, 1 Value guaranteed by characterization, not 100% tested in production. Test conditions specified in Table 10 Parameter Clock frequency ...
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... DC and AC parameters Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 34/44 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...
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... M95320, M95320-W, M95320-R Figure 17. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 5711 Rev 12 DC and AC parameters tSHSL tSHQZ AI01449f 35/44 ...
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... Doc ID 5711 Rev 12 M95320, M95320-W, M95320 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.011 0.0067 0.1929 0.189 0.2362 ...
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... M95320, M95320-W, M95320-R Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol 1. Values in inches are converted from mm and rounded to 4 decimal digits millimeters Typ. ...
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... Doc ID 5711 Rev 12 M95320, M95320-W, M95320 UFDFPN- must not be SS (1) inches Typ Min Max 0.0217 0.0177 0.0236 0.0008 0 0.002 0.0098 0.0079 0.0118 0.0787 ...
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... M95320, M95320-W, M95320-R 11 Part numbering Table 24. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 320 = 32 Kbit (4096 × 8) Operating voltage blank = V = 4 2 1 (1) Package MN = SO8 (150 mils width TSSOP8 (169 mils width MLP8 (2 × ...
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... Part numbering Table 25. Available M95320x products (package, voltage range, temperature grade) Package SO8 (MN) TSSOP (DW) MLP 2 × (MB) 40/44 M95320 M95320-W 4 5 5.5 V Range 6 Range 3 Range 3 Range 6 - Range Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R M95320-R 1 5.5 V Range 6 Range 6 Range 6 ...
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... I O 4.0 TSSOP8 connections added to DIP and SO connections M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and related characteristics added. 20MHz Clock rate added.TSSOP14 package removed and MLP8 package added. Description of Power On Reset: VCC Lock-Out Write Protect Product List summary table added ...
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... I and I parameters modified in CC CC1 (M95320-W, device grade Maximum frequency for M95320-W and M95640-W upgraded from 5 MHz MHz in the device grade 6 T characteristics (M95320-W, device grade 6) Table 27: Available M95640x products (package, voltage range, temperature grade): /PB process letter added, /P process letter removed. ...
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... Revision 20-Mar-2008 23-Jun-2008 17-Feb-2009 07-Dec-2009 Section 4.1: Supply voltage (V 10 MHz frequencies added to 9 device grade 3) and Table 19: AC characteristics (M95320-W, device grade 3). Small text changes. Section 4.1: Supply voltage (V Table 16: DC characteristics (M95320-R) 10 Figure 15: Serial input timing, output timing modified. ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 5711 Rev 12 M95320, M95320-W, M95320-R ...