M24C01-x STMICROELECTRONICS [STMicroelectronics], M24C01-x Datasheet - Page 15

• Manufacturer Part Number: M24C01-x
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24C08-x M24C04-x M24C02-x M24C01-x
3.6.3
Figure 8.
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in
can be used by the bus master.
The sequence, as shown in
●
●
●
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Table
Write mode sequences with WC = 0 (data write enabled)
14, but the typical time is shorter. To make use of this, a polling sequence
Dev Select
Dev Select
ACK
Figure
Doc ID 5067 Rev 18
Data in N
R/W
R/W
ACK
ACK
9, is:
Byte address
Byte address
ACK
ACK
ACK
Data in 1
Data in
ACK
ACK
Data in 2
Device operation
ACK
Data in 3
AI02804c
w
) is
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