24LC21-IP MICROCHIP [Microchip Technology], 24LC21-IP Datasheet - Page 8

• Manufacturer Part Number: 24LC21-IP
• Description: 1K 2.5V Dual Mode I 2 C Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

24LC21
FIGURE 4-2:
5.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.
DS21095F-page 8
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
VCLK
ACKNOWLEDGE POLLING
PAGE WRITE
S
S
T
A
R
T
CONTROL
BYTE
A
C
K
ADDRESS (n)
WORD
A
C
K
DATA n
FIGURE 5-1:
6.0
When using the 24LC21 in the Bi-Directional Mode, the
VCLK pin operates as the write protect control pin. Set-
ting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
array. Connecting the VCLK pin to V
24LC21 to operate as a serial ROM, although this con-
figuration would prevent using the device in the Trans-
mit-Only Mode.
WRITE PROTECTION
A
C
K
Initiate Write Cycle
Send Control Byte
DATA n + 1
Write Command
with R/W = 0
Acknowledge
Condition to
Send Stop
(ACK = 0)?
Did Device
Send Start
ACKNOWLEDGE POLLING
FLOW
Operation
Send
Next
YES
1996 Microchip Technology Inc.
A
C
K
DATA n + 15
SS
NO
would allow the
A
C
K
S
T
O
P
P