24LC21-IP MICROCHIP [Microchip Technology], 24LC21-IP Datasheet - Page 4

• Manufacturer Part Number: 24LC21-IP
• Description: 1K 2.5V Dual Mode I 2 C Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

24LC21
2.0
The 24LC21 operates in two modes, the Transmit-Only
Mode and the Bi-Directional Mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-Only Mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only
Mode is to remove power from the device.
2.1
The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-Only Mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on the SDA pin in 8 bit bytes, each followed by a
FIGURE 2-1:
FIGURE 2-2:
DS21095F-page 4
VCLK
VCLK
SDA
SCL
V
SDA
FUNCTIONAL DESCRIPTION
Transmit-Only Mode
SCL
CC
TRANSMIT ONLY MODE
DEVICE INITIALIZATION
T
H
VAA
IGH
T
T
1
VHIGH
VPU
I
MPEDANCE FOR
B
IT
T
1 (LSB)
VLOW
2
9
CLOCK CYCLES
T
VAA
N
ULL
ninth, null bit (see Figure 2-1). The clock source for the
Transmit-Only Mode is provided on the VCLK pin, and
a data bit is output on the rising edge on this pin. The
eight bits in each byte are transmitted most significant
bit first. Each byte within the memory array will be out-
put in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bi-Directional Mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-Only Mode.
2.2
After V
mit-Only Mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a high
impedance state. On the rising edge of the tenth clock
cycle, the device will output the first valid data bit which
will be the most significant bit of a byte. The device will
power up at an indeterminate byte address. (See
Figure 2-2).
8
B
IT
CC
Initialization Procedure
has stabilized, the device will be in the Trans-
9
B
IT
1 (MSB)
T
VAA
10
1996 Microchip Technology Inc.
B
IT
8
T
VAA
11
B
IT
7
B
IT
7