M-8880 CLARE [Clare, Inc.], M-8880 Datasheet - Page 3

• Manufacturer Part Number: M-8880
• Description: M-8880 DTMF Transceiver
• Manufacturer: CLARE [Clare, Inc.]

causes V
Provided that the signal condition is maintained (ESt remains
high) for the validation period (t
(V
corresponding 4-bit code (see Table 2) into the receive data reg-
ister.
At this point the StGT output is activated and drives V
StGT continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to settle, the
delayed steering output flag goes high, signaling that a received
tone pair has been registered. It is possible to monitor the status
of the delayed steering flag by checking the appropriate bit in the
status register. If interrupt mode has been selected, the IRQ/CP
pin will pull low when the delayed steering flag is active.
The contents of the output latch are updated on an active de-
layed steering transition. This data is presented to the 4-bit
bidirectional data bus when the receive data register is read.
40-406-00012, Rev. G
TSt
F
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
0 = logic low, 1 = logic high
LOW
) of the steering logic to register the tone pair, latching its
C
F
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
(see Figure 5) to rise as the capacitor discharges.
HIGH
Table 2 Tone Encoding/Decoding
Figure 5 Basic Steering Circuit
Digit
A
B
C
D
1
2
3
4
5
6
7
8
9
0
*
#
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
GTP
), V
C
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
reaches the threshold
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
C
to V
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DD
Page 3
M-8880
.
The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate signal in-
terruptions (dropout) too short to be considered a valid pause.
This capability, together with the ability to select the steering
time constants externally, allows the designer to tailor perfor-
mance to meet a wide variety of system requirements.
Guard Time Adjustment: The simple steering circuit shown in
Figure 5 is adequate for most applications. Component values
are chosen according to the formula:
The value of t
signal duration to be recognized by the receiver. A value for C1
of 0.1 F is recommended for most applications, leaving R1 to
be selected by the designer. Different steering arrangements
may be used to select independently the guard times for tone
present (t
meet system specifications that place both accept and reject
limits on both tone duration and interdigit pause. Guard time ad-
justment also allows the designer to tailor system parameters
such as talkoff and noise immunity. Increasing t
talkoff performance since it reduces the probability that tones
simulated by speech will maintain signal condition long enough
to be registered. Alternatively, a relatively short t
t
where fast acquisition time and immunity to tone dropouts are
required. Design information for guard time adjustment is shown
in Figure 6.
Call Progress Filter
A call progress (CP) mode can be selected, allowing the detec-
tion of various tones that identify the progress of a telephone call
on the network. The call progress tone input and DTMF input are
common; however, call progress tones can only be detected
when the CP mode has been selected. DTMF signals cannot be
DO
would be appropriate for extremely noisy environments
GTP
) and tone absent (t
Figure 6 Guard Time Adjustment
DP
is a device parameter and t
t
T
REC
ID
= t
= t
DA
DP
GTA
+ t
+ t
). This may be necessary to
GTA
GTP
REC
is the minimum
REC
REC
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with a long
improves