STA333BW_11 STMICROELECTRONICS [STMicroelectronics], STA333BW_11 Datasheet - Page 36
STA333BW_11
Manufacturer Part Number
STA333BW_11
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STA333BW_11.pdf
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Register description
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2.0 channels, two full-bridges (OCFG = 00)
Mapping:
Default modulation:
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On
channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this
configuration, volume control or EQ have no effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in
Figure 15. 2.0 channels (OCFG = 00) PWM slots
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A / 1B configured as ternary
FFX2A / 2B configured as ternary
FFX3A / 3B configured as lineout ternary
FFX4A / 4B configured as lineout ternary
OUT1A
OUT1A
OUT1B
OUT1B
OUT2A
OUT2A
OUT2B
OUT2B
OUT3A
OUT3A
OUT3B
OUT3B
OUT4A
OUT4A
OUT4B
OUT4B
Doc ID 13773 Rev 3
Figure
15.
STA333BW
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