AT89C51IC2-RLTIM ATMEL [ATMEL Corporation], AT89C51IC2-RLTIM Datasheet - Page 99
AT89C51IC2-RLTIM
Manufacturer Part Number
AT89C51IC2-RLTIM
Description
8-bit Flash Microcontroller with 2-wire Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51IC2-RLTIM.pdf
(147 pages)
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Registers
4301C–8051–06/06
Table 73. SSCON Register
SSCON - Synchronous Serial Control register (93h)
Table 74. SSDAT (095h) - Syncrhonous Serial Data register (read/write)
Number
Number
CR2
SD7
Bit
Bit
7
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
Mnemonic Description
Mnemonic Description
SSIE
SSIE
CR2
CR1
CR0
STA
ST0
SD6
SD7
SD6
SD5
SD4
SD3
SD2
Bit
Bit
AA
SI
6
6
Control Rate bit 2
See Table 67.
Synchronous Serial Interface Enable bit
Clear to disable SSLC.
Set to enable SSLC.
Start flag
Set to send a START condition on the bus.
Stop flag
Set to send a STOP condition on the bus.
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
Control Rate bit 1
See Table 67.
Control Rate bit 0
See Table 67.
Address bit 7 or Data bit 7.
Address bit 6 or Data bit 6.
Address bit 5 or Data bit 5.
Address bit 4 or Data bit 4.
Address bit 3 or Data bit 3.
Address bit 2 or Data bit 2.
STA
SD5
5
5
STO
SD4
4
4
SD3
SI
3
3
SD2
AA
2
2
AT89C51IC2
CR1
SD1
1
1
CR0
SD0
0
0
99
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