MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 86

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Internal Clock Generator (ICG) Module)
7.3.4.2 Internal Clock Activity Detector
The internal clock activity detector, shown in
low-frequency base clock (IBASE) every time the external reference (EREF) is low. Since EREF is less
than half the frequency of IBASE, this should occur every time. If it does not occur two consecutive times,
the internal clock inactivity indicator (IOFF) is set. IOFF will be cleared the next time there is a falling edge
of IBASE while EREF is low.
The internal clock stable bit (ICGS) is also generated in the internal clock activity detector. ICGS is set
when the internal clock generator’s filter stable signal (FICGS) indicates that IBASE is within about 5
percent of the target 307.2 kHz ± 25 percent for two consecutive measurements. ICGS is cleared when
FICGS is clear, the internal clock generator is turned off or is in stop mode (ICGEN is clear), or when IOFF
is set.
7.3.4.3 External Clock Activity Detector
The external clock activity detector, shown in
clock (ECLK) every time the internal reference (IREF) is low. Since IREF is less than half the frequency
of ECLK, this should occur every time. If it does not occur two consecutive times, the external clock
inactivity indicator (EOFF) is set. EOFF will be cleared the next time there is a falling edge of ECLK while
IREF is low.
The external clock stable bit (ECGS) is also generated in the external clock activity detector. ECGS is set
on a falling edge of the external stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the
external clock generator on bit is set, or the MCU exits stop mode (ECGEN = 1) if the external crystal
enable (EXTXTALEN) in the CONFIG2 register is set, or 16 cycles when EXTXTALEN is clear. ECGS is
cleared when the external clock generator is turned off or in stop mode (ECGEN is clear) or when EOFF
is set.
86
OUTPUT CLOCK
DLF MEASURE
IBASE
CMON
ICGEN
FICGS
EREF
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
NAME
NAME
Figure 7-6. Internal Clock Activity Detector
D
CK
DFFRS
CONFIG2 REGISTER BIT
TOP LEVEL SIGNAL
R
S
Q
CK
1/4
R
Figure
Figure
Q
7-7, looks for at least one falling edge on the external
7-6, looks for at least one falling edge on the
D
CK
DFFRR
R
R
Q
D
CK
DFFRR
NAME
NAME
R
R
Q
MODULE SIGNAL
REGISTER BIT
ICGS
IOFF
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