UJA1078 NXP [NXP Semiconductors], UJA1078 Datasheet - Page 18

• Manufacturer Part Number: UJA1078
• Description: High-speed CAN/dual LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
UJA1078_2
Product data sheet
6.4.2 Watchdog Timeout behavior
6.4.3 Watchdog Off behavior
6.5 System reset
The watchdog runs continuously in Timeout mode. It can be reset at any time by a
watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set. If a CI is
already pending, a system reset is performed.
The watchdog is in Timeout mode when pin WDOFF is LOW and:
The watchdog is disabled in this state.
The watchdog is in Off mode when:
The following events will cause the SBC to perform a system reset:
A watchdog overflow in Timeout mode requests a cyclic interrupt (CI), if a CI is not already
pending.
The UJA1078 provides three signals for dealing with reset events:
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the SBC is in Standby mode and bit WMC = 0 or
the SBC is in Off, Overtemp or Sleep modes
the SBC is in Standby mode and bit WMC = 1
the SBC is in any mode and the WDOFF pin is HIGH
V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN
pin)
An external reset (RSTN forced LOW)
Watchdog overflow (Window mode)
Watchdog overflow in Timeout mode with cyclic interrupt (CI) pending
Watchdog triggered too early in Window mode
WMC value changed in Normal mode
WDOFF pin state changed
SBC goes to Sleep mode (MC set to 01; see
SBC goes to Sleep mode (MC set to 01; see
STBCC = STBCL1 = STBCL2 = WIC1 = WIC2 = 0
SBC goes to Sleep mode (MC set to 01; see
Software reset (SWR = 1)
SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor
on RSTN pin)
RSTN input/output for performing a global ECU system reset or forcing an external
reset
EN pin, a fail-safe global enable output
LIMP pin, a fail-safe limp home output
the SBC is in Normal mode and bit WMC = 1
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
High-speed CAN/dual LIN core system basis chip
Table
Table
Table
5) while INTN is driven LOW
5) while
5) while wake-up pending
UJA1078
© NXP B.V. 2010. All rights reserved.
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