MCZ33784EF/R2- FREESCALE [Freescale Semiconductor, Inc], MCZ33784EF/R2- Datasheet - Page 15

• Manufacturer Part Number: MCZ33784EF/R2-
• Description: DSI 2.02 Sensor Interface
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

COMMUNICATION FORMAT
separated by a frame delay. Transfers are full duplex.
Command messages from the master occur at the same time
as responses from the slaves. Slave responses to commands
occur during the next command message. This allows slaves
Analog Integrated Circuit Device Data
Freescale Semiconductor
DBUS messages are composed of individual words
10MHz Clock
Received Message
Bus Controller
From MASTER
Load Enable
10MHz Clock
Check
Data Clock
CRC
Figure 6. DBUS Slave Logic Block Diagram
Data Clock
Figure 7. Bus Traffic Example
Data
Latch
FORMAT CONTROL
Command Buffer
Response Shifter
CRC Generator
DBUS Registers
I/O CONTROL
REQ STATUS
REQ AN0
REQ AN1
REQ ID
CLEAR
time to decode the command, retrieve the information, and
prepare to send it to the master. A bus traffic example is
shown in
minimum frame delay followed by a command after a longer
delay.
TEST
INIT
The example shows three commands separated by the
Figure
7.
DATA OUT [2:0]
I/O [2:0]
AD_SEL
AD_DATA [9:0]
TEST
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SEL
I
Response
ON
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