LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 60

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Notes:
Rev. 03-28-07
For edge triggered systems, the Interrupt Service Routine should clear the Interrupt Mask Register, and only
enable the appropriate interrupts after the interrupt source is serviced (acknowledged).
b)
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
1.
2.
3.
4.
5.
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit
set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read
from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the
FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
The previous empty condition is cleared (acknowledged)
TXUNRN - Transmit under-run
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
DATASHEET
Page 60
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
SMSC LAN91C965v&3v