LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 55

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Note:
SMSC LAN91C965v&3v
FAILED
REMPTY
RESERVED
TEMPTY
I/O SPACE - BANK2
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is
accessible through the TX area. Some MMU commands use the number stored in this register as the
packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
RESERVED – This bit is reserved.
I/O SPACE - BANK2
FAILED - A ”0” indicates a successful allocation completion. If the allocation fails the bit is set and only
cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For
polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is
synchronized to the read operation. Sequence:
1.
2.
3.
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request.
The value is only valid if the FAILED bit is clear.
For software compatibility with future versions, the value read from the ARR after an allocation request is
intended to be written into the PNR as is, without masking higher bits (provided FAILED = “0”).
I/O SPACE - BANK2
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO.
The packet numbers to be processed by the interrupt service routines are read from this register.
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the
Interrupt Status Register.
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid
if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 6) or 8).
OFFSET
OFFSET
OFFSET
1
1
1
Allocate Command
Poll ALLOC_INT bit until set
Read Allocation Result Register
0
2
3
4
0
0
0
0
ALLOCATION RESULT REGISTER
PACKET NUMBER REGISTER
FIFO PORTS REGISTER
0
0
0
0
DATASHEET
NAME
NAME
NAME
0
0
0
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
ALLOCATED PACKET NUMBER
PACKET NUMBER AT TX AREA
RX FIFO PACKET NUMBER
TX FIFO PACKET NUMBER
0
0
0
0
READ/WRITE
READ ONLY
READ ONLY
0
0
0
TYPE
TYPE
TYPE
0
0
0
0
0
SYMBOL
SYMBOL
SYMBOL
FIFO
ARR
PNR
0
0
0
0
Rev. 03-28-07