MC68HC705SR3 MOTOROLA [Motorola, Inc], MC68HC705SR3 Datasheet - Page 41

• Manufacturer Part Number: MC68HC705SR3
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units
• Manufacturer: MOTOROLA [Motorola, Inc]

5.2.2
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the
I-bit allows interrupt processing to occur.
Note:
5.2.2.1
The external interrupt IRQ is controlled by two bits in the Miscellaneous Control Register ($0C).
INTE — INTerrupt Enable
The external IRQ is default enabled at power-on reset.
INTO — INTerrupt Option
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the Condition Code Register is
set. This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents in $1FFA-$1FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
MC68HC05SR3
Miscellaneous Control Register
1 (set)
0 (clear) –
1 (set)
0 (clear) –
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
Maskable Hardware Interrupts
External Interrupt (IRQ)
Freescale Semiconductor, Inc.
–
–
For More Information On This Product,
External interrupt IRQ is enabled.
External interrupt is disabled.
Negative-edge sensitive triggering for IRQ.
Negative-level sensitive triggering for IRQ.
Address bit 7
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$0C
RESETS AND INTERRUPTS
KBIE
KBIC
bit 6
INTO
bit 5
INTE
bit 4
LVRE
bit 3
bit 2
SM
IRQ2F IRQ2E 0001 0000
bit 1
bit 0
MOTOROLA
on reset
State
TPG
5-5
5