AIC1574 AIC [Analog Intergrations Corporation], AIC1574 Datasheet - Page 10

• Manufacturer Part Number: AIC1574
• Description: 5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers
• Manufacturer: AIC [Analog Intergrations Corporation]

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PIN DESCRIPTION
Pin 1: DRIVE2: Connect this pin to the Gate of
Pin 2 :
Pin 7: VID4:
Pin 6: VID3:
Pin 5: VID2:
Pin 4: VID1:
Pin 3: VID0:
Pin 8: PGOOD: Power
the external N-MOS to supply
AGP power.
FIX:
voltage is pulled high, enabling
fixed output voltage operation for
1.5V and 1.8V linear regulators. If
connect this pin to Ground, the
new output voltage set by external
resistors R
tween VSEN and GND) and R
(Connected between VSEN and
VOUT) .
5bit DAC voltage select pin. TTL-
compatible inputs used to set the
internal voltage reference VDAC.
When left open, these pins are in-
ternally pulled up to 5V and
provide logic ones. The level of
VDAC sets the converter output
voltage as well as the PGOOD
and OVP thresholds.
Table 1 specifies the VDAC volt-
age for the 32 combinations of
DAC inputs.
PGOOD is an open drain output.
This pin is pulled low when the
converter output is ±10% out of
the VDAC reference voltage and
V
OUT
1.265V
good
GND
Left this pin open, its
(Connected be-
indicator
R
(R
GND
GND
R
OUT
pin.
OUT
)
Pin 9 :
Pin 10:VSEN2: Connect this pin to the output of
Pin 11:SELECT: This pin determines the output
the other outputs are below their
under-voltage
PGOOD output is open for VID
codes that inhibit operation. See
Table 1.
logic level high signal applied
this pin immediately discharges
the soft-start capacitors, dis-
abling all the outputs. Dedicated
internal circuitry insures the core
output voltage does not go nec-
tive during this process. When
re-enabled, this IC undergoes a
new soft-start cycle. Left open,
this pin is pulled low by an inter-
nal pull-down resistor, enabling
operation.
the AGP linear regulator. The
voltage at this pin is regulated to
the 1.5V/3.3V predetermined by
the logic Low/High level ststus of
the SELECT pin. This pin is also
monitored
events.
voltage of the AGP bus linear
regulator. A low TTL input sets
the output voltage to 1.5V, while
a high input sets the output volt-
age to 3.3V.
SD:
A
for
AIC1574
thresholds.
TTL-compatibe
under-voltage
10
The