ADV212 AD [Analog Devices], ADV212 Datasheet - Page 35

• Manufacturer Part Number: ADV212
• Description: JPEG 2000 Video Codec
• Manufacturer: AD [Analog Devices]

DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM[5] pin is connected to the same GPIO on the host.
32-BIT HOST CPU
DATA[31:0]
ADDR[3:0]
DREQ
DACK
DREQ
DACK
G I/O
ACK
ACK
IRQ
IRQ
WR
WR
CS
RD
CS
RD
Figure 34. Decode—Multichip Master/Slave Application
ADV212_1_MASTER
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
ADV212_2_SLAVE
VDATA[11:2]
VDATA[11:2]
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VSYNC
HSYNC
HSYNC
VSYNC
MCLK
FIELD
MCLK
FIELD
VCLK
VCLK
Y
CbCr
In a slave/slave configuration, the common HVF for both
ADV212s is generated by an external house sync and each
SCOMM[5] is connected to the same GPIO output on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
74.25MHz
OSC
CbCr
Y
CLKIN
Y[9:0]
C[9:0]
10-BIT SD/HD
ADV7321A
ENCODER
VIDEO
1080i
VIDEO OUT
ADV212