TP3054-X NSC [National Semiconductor], TP3054-X Datasheet - Page 6

• Manufacturer Part Number: TP3054-X
• Description: Extended Temperature Serial Interface CODEC/Filter COMBO Family
• Manufacturer: NSC [National Semiconductor]

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RM
FM
PB
RB
FB
WMH
WML
SBFM
SFFM
WBH
WBL
HBFL
HBFS
SFB
DBD
DBTS
DZC
DZF
SDB
HBD
SF
HF
HBFl
WFL
Symbol
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
−40˚C to +85˚C by correlation with 100% electrical testing at T
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
+5.0V, V
Conventions section for test methods information.
PM
BB
Frequency of Master Clocks
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
Rise Time of Bit Clock
Fall Time of Bit Clock
Width of Master Clock High
Width of Master Clock Low
Set-Up Time from BCLK
to MCLK
Setup Time from FS
MCLK
Width of Bit Clock High
Width of Bit Clock Low
Holding Time from Bit Clock
Low to Frame Sync
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
Delay Time from BCLK
to Data Valid
Delay Time to TS
Delay Time from BCLK
Data Output Disabled
Delay Time to Valid Data from
FS
Comes Later
Set-Up Time from D
BCLK
Hold Time from BCLK
D
Set-Up Time from FS
BCLK
Hold Time from BCLK
to FS
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FS
Minimum Width of the Frame
Sync Pulse (Low Level)
= –5.0V, T
R
X
Invalid
X
or BCLK
X/R
or FS
R/X
X/R
X
Falling Edge
X
Low
Low
Low
Falling Edge
R
A
)
Parameter
X
= 25˚C. All timing parameters are assured at V
, Whichever
X
Low
R
X
X/R
R/X
X/R
High to
Valid to
X
X
X
High
Low to
to
Low to
Low
High
Depends on the Device Used and the
BCLK
MCLK
MCLK
MCLK
BCLK
BCLK
MCLK
MCLK
First Bit Clock after
the Leading Edge
of FS
Long Frame Only
V
V
Long Frame Only
Short Frame Only
Long Frame Only
Load=150 pF plus 2 LSTTL Loads
Load=150 pF plus 2 LSTTL Loads
C
C
Short Frame Sync Pulse (1 Bit Clock
Period Long)
Short Frame Sync Pulse (1 Bit Clock
Period Long)
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
64k Bit/s Operating Mode
IH
IL
L
L
=0 pF to 150 pF
=0 pF to 150 pF
=0.6V
=2.2V
X
R
X
X
X
X
X
X
X
/CLKSEL Pin.
and BCLK
and BCLK
and MCLK
and MCLK
and MCLK
and MCLK
and MCLK
A
6
Conditions
= 25˚C. All other limits are assured by correlation with other
R
R
R
R
R
R
R
OH
= 2.0V and V
Short Frame
Long Frame
CC
= +5.0V
OL
= 0.7V. See Definitions and Timing
±
5%, V
Min
485
160
160
100
125
100
160
160
115
100
100
160
50
20
50
50
50
0
0
0
BB
= −5.0V
1.536
1.544
2.048
Typ
488
±
5%; T
15725
Max
140
140
165
165
50
50
50
50
CC
A
=
=
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns