TP3054-X NSC [National Semiconductor], TP3054-X Datasheet - Page 3

• Manufacturer Part Number: TP3054-X
• Description: Extended Temperature Serial Interface CODEC/Filter COMBO Family
• Manufacturer: NSC [National Semiconductor]

Pin Descriptions
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initial-
izes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK
present. Thus, 2 power-down control modes are available.
The first is to pull the MCLK
to hold both FS
device will power-down approximately 1 ms after the last
FS
FS
in the high impedance state until the second FS
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLK
and the MCLK
control. A low level on MCLK
and a high level powers down the device. In either case,
MCLK
transmit and receive circuits. A bit clock must also be applied
to BCLK
proper internal divider for a master clock of 1.536 MHz,
1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the
device automatically compensates for the 193rd clock pulse
each frame.
MCLK
FS
BCLK
D
TS
GS
VF
VF
X
X
R
X
X
X
X
X
pulse. The TRI-STATE PCM data output, D
Symbol
I
I
or FS
−
+
R
X
X
X
/PDN pin and FS
X
will be selected as the master clock for both the
and the BCLK
R
pulse. Power-up will occur on the first FS
R
/PDN pin can be used as a power-down
X
Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
performance is realized from
synchronous operation.
Transmit frame sync pulse input which
enables BCLK
data on D
train, see Figure 2 and Figure 3 for
timing details.
The bit clock which shifts out the PCM
data on D
2.048 MHz, but must be synchronous
with MCLK
The TRI-STATE
which is enabled by FS
Open drain output which pulses low
during the encoder time slot.
Analog output of the transmit input
amplifier. Used to externally set gain.
Inverting input of the transmit input
amplifier.
Non-inverting input of the transmit input
amplifier.
and FS
R
/CLKSEL can be used to select the
X
R
R
X
X
/PDN pin high; the alternative is
X
and/or FS
inputs continuously low — the
. FS
. May vary from 64 kHz to
R
(Continued)
.
/PDN powers up the device
X
X
Function
®
to shift out the PCM
is an 8 kHz pulse
PCM data output
R
X
pulses must be
.
R
. Best
X
X
, will remain
X
and VF
pulse.
X
R
or
O
X
3
With a fixed level on the BCLK
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
CLKSEL. In this synchronous mode, the bit clock, BCLK
may be from 64 kHz to 2.048 MHz, but must be synchronous
with MCLK
Each FS
data from the previous encode cycle is shifted out of the
enabled D
clock periods, the TRI-STATE D
impedance state. With an FS
via the D
if running). FS
MCLK
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK
with MCLK
logic levels to the MCLK
connect MCLK
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS
with MCLK
and must be synchronous with BCLK
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK
64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS
timing relationships specified in Figure 2. With FS
during a falling edge of BCLK
BCLK
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the D
of BCLK
edge of BCLK
falling edges latch in the seven remaining bits. All four de-
vices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.
Clocked
0
1
BCLK
X
TABLE 1. Selection of Master Clock Frequencies
starts each encoding cycle and must be synchronous
X
X/R
enables the D
R
R
X
R
.
/CLKSEL
X
X
X
X
input on the negative edge of BCLK
(BCLK
pulse begins the encoding cycle and the PCM
X
output on the positive edge of BCLK
, which is easily achieved by applying only static
.
and FS
and BCLK
R
X
X
X
output. With FS
latches in the sign bit. The following seven
to all internal MCLK
X
and FS
R
in synchronous mode), the next falling
, must be one bit clock period long, with
X
1.536 MHz or
TRI-STATE output buffer, which will
X
2.048 MHz
1.544 MHz
2.048 MHz
R
. FS
TP3057
/PDN pin. This will automatically
R
X
Frequency Selected
and BCLK
R
R
R
must be synchronous with
X
/CLKSEL pin, BCLK
pulse, PCM data is latched
starts each decoding cycle
X
R
Master Clock
output is returned to a high
, the next rising edge of
X
high during a falling edge
R
and MCLK
should be synchronous
R
R
. BCLK
R
functions (see Pin
may operate from
1.536 MHz or
1.536 MHz or
1.544 MHz
2.048 MHz
1.544 MHz
TP3054
R
X
X
R
www.national.com
. After 8 bit
(or BCLK
must be a
must be
X
X
will be
high
R
X
R
/
,